AD9249 datasheet(25/37 Pages) AD

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AD9249

Data Sheet

Rev. 0 | Page 24 of 36

The PN sequence short pattern produces a pseudorandom bit

sequence that repeats itself every 29 − 1 or 511 bits. Refer to

Section 5.1 of the ITU-T 0.150 (05/96) standard for a description

of the PN sequence and how it is generated. The seed value is all

1s (see Table 12 for the initial values). The output is a parallel

representation of the serial PN9 sequence in MSB-first format.

The first output word is the first 14 bits of the PN9 sequence in

MSB aligned form.

Table 12. PN Sequence

Sequence

Initial

Value

Next Three Output Samples

(MSB First) Twos Complement

PN Sequence Short

0x1FE0

0x1DF1, 0x3CC8, 0x294E

PN Sequence Long

0x1FFF

0x1FE0, 0x2001, 0x1C00

The PN sequence long pattern produces a pseudorandom

bit sequence that repeats itself every 223 − 1 or 8,388,607 bits.

Refer to Section 5.6 of the ITU-T 0.150 (05/96) standard for a

description of the PN sequence and how it is generated. The

seed value is all 1s (see Table 12 for the initial values) and the

AD9249 inverts the bit stream with relation to the ITU standard.

The output is a parallel representation of the serial PN23 sequence

in MSB-first format. The first output word is the first 14 bits of the

PN23 sequence in MSB aligned format.

Consult the Memory Map section for information on how to

change these additional digital output timing features through

the SPI.

SDIO/DFS Pin

For applications that do not require SPI mode operation, the CSB1

and CSB2 pins are tied to AVDD, and the SDIO/DFS pin controls

the output data format select as described in Table 13.

Table 13. Output Data Format Select Pin Settings

DFS Pin Voltage

Output Mode

AVDD

Twos complement

GND (Default)

Offset binary

SCLK/DTP Pin

The SCLK/DTP pin can enable a single digital test pattern if it

and the CSB1 and CSB2 pins are held high during device power-

up. When SCLK/DTP is tied to AVDD, the ADC channel outputs

shift out the following pattern: 10 0000 0000 0000. The FCO±1,

FCO±2, DCO±1, and DCO±2 pins function normally while all

channels shift out the repeatable test pattern. This pattern allows

the user to perform timing alignment adjustments among the

FCO±1, FCO±2, DCO±1, DCO±2, and output data. The SCLK/

DTP pin has an internal 30 kΩ resistor to GND. It can be left

unconnected for normal operation.

Table 14. Digital Test Pattern Pin Settings

Selected DTP

DTP Voltage

Resulting D±xx

Normal Operation

No connect

Normal operation

DTP

AVDD

10 0000 0000 0000

Additional and custom test patterns can also be observed when

commanded from the SPI port. Consult the Memory Map section

for information about the options that are available.

CSB1 and CSB2 Pins

The CSB1 and CSB2 pins are tied to AVDD for applications that

do not require SPI mode operation. Tying CSB1 and CSB2 high

causes all SCLK and SDIO SPI communication information to be

ignored.

CSB1 selects/deselects SPI circuitry affecting outputs D±A1 to

D±H1 (Bank 1). CSB2 selects/deselects SPI circuitry affecting

outputs D±A2 to D±H2 (Bank 2).

It is recommended that CSB1 and CSB2 be controlled with the

same signal; that is, tie them together. In this way, whether tying

them to AVDD or selecting SPI functionality, both banks of ADCs

are controlled identically and are always in the same state.

RBIAS1 and RBIAS2 Pins

To set the internal core bias current of the ADC, place a 10.0 kΩ,

1% tolerance resistor to ground at each of the RBIAS1 and

RBIAS2 pins.

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