Data Sheet

AD9249

Rev. 0 | Page 23 of 36

Two output clock types are provided to assist in capturing data

from the AD9249. DCO±1 and DCO±2 clock the output data,

and their frequency is equal to 7× the sample clock (CLK±) rate

for the default mode of operation. Data is clocked out of the

AD9249 and must be captured on the rising and falling edges of

the DCO that supports double data rate (DDR) capturing. DCO±1

is used to capture the D±x1 (Bank 1) data; DCO±2 is used to

capture the D±x2 (Bank 2) data. FCO±1 and FCO±2 signal the

start of a new output byte, and the frequency is equal to the sample

clock rate. FCO±1 frames the D±x1 (Bank 1) data; FCO±2

frames the D±x2 (Bank 2) data (see Figure 3 and Figure 4).

When the SPI is used, the DCO phase can be adjusted in 60°

increments relative to one data cycle (30° relative to one DCO

cycle). This enables the user to refine system timing margins, if

required. The default DCO±1 and DCO±2 to output data edge

timing, as shown in Figure 3, is 180° relative to one data cycle

(90° relative to one DCO cycle).

A 12-bit serial stream can also be initiated from the SPI. This

allows the user to implement and test compatibility to lower

resolution systems. When changing the resolution to a 12-bit

serial stream, the data stream is shortened. See Figure 4 for the

12-bit example.

In default mode, as shown in Figure 3, the MSB is first in the

data output serial stream. This can be inverted so that the LSB is

first in the data output serial stream by using the SPI.

There are 12 digital output test pattern options available that can

be initiated through the SPI. This is a useful feature when validating

receiver capture and timing (see Table 11 for the output bit

sequencing options that are available). Some test patterns have

two serial sequential words and can alternate in various ways,

depending on the test pattern chosen. Note that some patterns

do not adhere to the data format select option. In addition, custom

user-defined test patterns can be assigned in Register 0x19,

Register 0x1A, Register 0x1B, and Register 0x1C.

Table 11. Flexible Output Test Modes

OutputTest

Mode Bit

Sequence

(Reg. 0x0D)

Pattern Name

Digital Output Word 11

Digital Output Word 21

Subject

to Data

Format

Select1

Notes

0000

Off (default)

N/A

N/A

N/A

0001

Midscale short

1000 0000 0000 (12-bit)

N/A

Yes

Offset binary code shown

10 0000 0000 0000 (14-bit)

0010

+Full-scale short

1111 1111 1111 (12-bit)

N/A

Yes

Offset binary code shown

11 1111 1111 1111 (14-bit)

0011

−Full-scale short

0000 0000 0000 (12-bit)

N/A

Yes

Offset binary code shown

00 0000 0000 0000 (14-bit)

0100

Checkerboard

1010 1010 1010 (12-bit)

0101 0101 0101 (12-bit)

No

10 1010 1010 1010 (14-bit)

01 0101 0101 0101 (14-bit)

0101

PN sequence long2

N/A

N/A

Yes

PN23

ITU 0.150

0110

PN sequence short2

N/A

N/A

Yes

PN9

ITU 0.150

0111

One-/zero-word

toggle

1111 1111 1111 (12-bit)

0000 0000 0000 (12-bit)

No

11 1111 1111 1111 (14-bit)

00 0000 0000 0000 (14-bit)

1000

User input

Register 0x19 to Register 0x1A

Register 0x1B to Register 0x1C

No

1001

1-/0-bit toggle

1010 1010 1010 (12-bit)

N/A

No

10 1010 1010 1010 (14-bit)

1010

1× sync

0000 0011 1111 (12-bit)

N/A

No

00 0000 0111 1111 (14-bit)

1011

One bit high

1000 0000 0000 (12-bit)

N/A

No

Pattern associated with

the external pin

10 0000 0000 0000 (14-bit)

1100

Mixed frequency

1010 0011 0011 (12-bit)

N/A

No

10 1000 0110 0111 (14-bit)

1

N/A means not applicable.

2

All test mode options except PN sequence short and PN sequence long can support 12-bit to 14-bit word lengths to verify data capture to the receiver.