AD9689 datasheet(64/134 Pages) AD

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AD9689

Data Sheet

Rev. A | Page 64 of 134

DDC EXAMPLE CONFIGURATIONS

Table 27 describes the register settings for multiple DDC example configurations.

Table 27. DDC Example Configurations (Per ADC Channel Pair)

Chip

Application

Layer

Chip

Decimation

Ratio

DDC

Input

Type

DDC

Output

Type

Bandwidth

Per DDC1

No. of Virtual

Converters

Required

One DDC

Complex

40% × fS

0x0200 = 0x01 (one DDC; I/Q selected)

0x0201 = 0x01 (chip decimate by 2)

0x0310 = 0x83 (complex mixer; 0 dB gain; variable IF;

complex outputs; HB1 filter)

0x0311 = 0x04 (DDC I Input = ADC Channel A; DDC Q

input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

Two DDCs

Complex

20% × fS

0x0200 = 0x02 (two DDCs; I/Q selected)

0x0201 = 0x02 (chip decimate by 4)

0x0310, 0x0330 = 0x80 (complex mixer; 0 dB gain;

variable IF; complex outputs; HB2 + HB1 filters)

0x0311, 0x0331 = 0x04 (DDC I input = ADC Channel A;

DDC Q input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW

and POW set as required by application for DDC1

Two DDCs

Complex

Real

10% × fS

0x0200 = 0x22 (two DDCs; I only selected)

0x0201 = 0x02 (chip decimate by 4)

0x0310, 0x0330 = 0x89 (complex mixer; 0 dB gain;

variable IF; real output; HB3 + HB2 + HB1 filters)

0x0311, 0x0331 = 0x04 (DDC I Input = ADC Channel A;

DDC Q input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW

and POW set as required by application for DDC1

Two DDCs

Real

10% × fS

0x0200 = 0x22 (two DDCs; I only selected)

0x0201 = 0x02 (chip decimate by 4)

0x0310, 0x0330 = 0x49 (real mixer; 6 dB gain; variable IF;

real output; HB3 + HB2 + HB1 filters)

0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q

input = ADC Channel A)

0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q

input = ADC Channel B)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,

0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW

and POW set as required by application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,

0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW

and POW set as required by application for DDC1

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