AD9689 datasheet(9/134 Pages) AD

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Data Sheet

AD9689

Rev. A | Page 9 of 134

SWITCHING SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,

SPIVDD = 1.9 V, default SPI settings, −10°C ≤ TJ ≤ +120°C,1 unless otherwise noted. Typical specifications represent performance at

TJ = 70°C (TA = 25°C).

Table 4.

2.0 GSPS

2.6 GSPS

Parameter

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK

Clock Rate at CLK+/CLK− Pins

GHz

Sample Rate2

1200

2000

2100

1900

2600

2700

MSPS

Clock Pulse Width High

238.096

185.185

Clock Pulse Width Low

238.096

185.185

OUTPUT PARAMETERS

Unit Interval (UI)3

62.5

66.67

592.6

62.5

66.67

592.6

Rise Time (tR) (20% to 80% into 100 Ω Load)

Fall Time (tF) (20% to 80% into 100 Ω Load)

Phase-Locked Loop (PLL) Lock Time

Data Rate per Channel (Nonreturn to Zero)4

1.6875

Gbps

LATENCY 5

Pipeline Latency6

Clock cycles

Fast Detect Latency

Clock cycles

NCO Channel Selection to Output

Clock cycles

WAKE-UP TIME

Standby

400

µs

Power-Down

APERTURE

Delay (tA)

250

Uncertainty (Jitter, tJ)

fs rms

Out of Range Recovery Time

Clock cycles

The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C.

The maximum sample rate is the clock rate after the divider.

Baud rate = 1/UI. A subset of this range can be supported.

Default L = 8. This number can be changed based on the sample rate and decimation ratio.

No DDCs used. L = 8, M = 2, and F = 1.

Refer to the Latency section for more details.

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