AD9689 datasheet(72/134 Pages) AD

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AD9689

Data Sheet

Rev. A | Page 72 of 134

ADC TEST PATTERNS

(0x0550,

0x0551 TO 0x0558)

JESD204B LONG

TRANSPORT TEST

PATTERN

0x0571[5]

JESD204B

INTERFACE TEST

PATTERN

(0x0573,

0x0551 TO 0x0558)

JESD204B DATA

LINK LAYER TEST

PATTERNS

0x0574[2:0]

JESD204B SAMPLE

CONSTRUCTION

TAIL BITS

0x0571[6]

A13

MSB

LSB

A12

A11

A10

A13

A12

A11

A10

MSB

LSB

CONTROL BITS

ADC

SERDOUT0±

SERDOUT3±

SERDOUT2±

SERDOUT1±

FRAME

CONSTRUCTION

SERIALIZER

SYMBOL0 SYMBOL1

SCRAMBLER

1 + x14 + x15

(OPTIONAL)

a b

i j a b

i j

a b c d e f g h i j

MSB

LSB

8-BIT/

10-BIT

ENCODER

Figure 132. ADC Output Datapath Showing Data Framing

SYSREF±

SYNCINB±

PROCESSED

SAMPLES

FROM ADC

SAMPLE

CONSTRUCTION

FRAME

CONSTRUCTION

8-BIT/10-BIT

ENCODER

CROSSBAR

MUX

SCRAMBLER

SERIALIZER

ALIGNMENT

CHARACTER

GENERATION

OUTPUT

TRANSPORT

LAYER

DATA LINK

LAYER

PHYSICAL

LAYER

Figure 133. Data Flow

FUNCTIONAL OVERVIEW

The block diagram in Figure 133 shows the flow of data through

the JESD204B hardware from the sample input to the physical

output. The processing can be divided into layers that are

derived from the open-source initiative (OSI) model widely

used to describe the abstraction layers of communications

systems. These layers are the transport layer, data link layer,

and physical layer (serializer and output driver).

Transport Layer

The transport layer handles packing the data (consisting of

samples and optional control bits) into JESD204B frames that

are mapped to 8-bit octets. These octets are sent to the data link

layer. The transport layer mapping is controlled by rules derived

from the link parameters. Tail bits are added to fill gaps where

required. The following equation can be used to determine the

number of tail bits within a sample (JESD204B word):

T = N΄ − N − CS

Data Link Layer

The data link layer is responsible for the low level functions

of passing data across the link. These functions include optionally

scrambling the data, inserting control characters for multichip

synchronization/lane alignment/monitoring, and encoding

8-bit octets into 10-bit symbols. The data link layer is also

responsible for sending the initial lane alignment sequence

(ILAS), which contains the link configuration data used by the

receiver to verify the settings in the transport layer.

Physical Layer

The physical layer consists of the high speed circuitry clocked at

the serial clock rate. In this layer, parallel data is converted into

one, two, four, or eight lanes of high speed differential serial data.

JESD204B LINK ESTABLISHMENT

The AD9689 JESD204B transmitter (Tx) interface operates in

Subclass 1 as defined in the JEDEC Standard JESD204B

(July 2011 specification). The link establishment process is

divided into the following steps: code group synchronization

(CGS) and SYNCINB±, initial lane alignment sequence, and user

data and error correction.

CGS and SYNCINB±

CGS is the process in which the JESD204B receiver finds the

boundaries between the 10-bit symbols in the stream of data.

During the CGS phase, the JESD204B transmit block transmits

/K28.5/ characters. The receiver must locate /K28.5/ characters

in its input data stream using clock and data recovery (CDR)

techniques.

The receiver issues a synchronization request by asserting the

SYNCINB± pin of the AD9689 low. The JESD204B Tx then begins

sending /K/ characters. After the receiver synchronizes, it waits for

the correct reception of at least four consecutive /K/ symbols. It

then deasserts SYNCINB±. The AD9689 then transmits an ILAS

on the following LMFC boundary.

For more information on the code group synchronization

phase, refer to the JEDEC Standard JESD204B, July 2011,

Section 5.3.3.1.

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