 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AT40K Datasheet(PDF) 35 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
AT40K Datasheet(HTML) 35 Page - ATMEL Corporation |
|
|
35 / 67 page  35 AT40K/AT40KLV Series FPGA 0896C–FPGA–04/02 AC Timing Characteristics – 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: VCC = 3.0V, temperature = 70°C Minimum times based on best case: VCC = 3.6V, temperature = 0°C Maximum delays are the average of tPDLH and tPDHL. Clocks and Reset Input buffers are measured from a V IH of 1.5V at the input pad to the internal VIH of 50% of VCC. Maximum times for clock input buffers and internal drivers are measured for rising edge delays only. Cell Function Parameter Path Device -3 Units Notes Global Clocks and Set/Reset GCK Input Buffer t PD (Maximum) pad -> clock pad -> clock pad -> clock pad -> clock AT40K05LV AT40K10LV AT40K20LV AT40K40LV 1.3 1.5 1.6 1.9 ns ns ns ns Rising edge clock FCK Input Buffer t PD (Maximum) pad -> clock pad -> clock pad -> clock pad -> clock AT40K05LV AT40K10LV AT40K20LV AT40K40LV 0.7 0.8 0.8 0.9 ns ns ns ns Rising edge clock Clock Column Driver tPD (Maximum) clock -> colclk clock -> colclk clock -> colclk clock -> colclk AT40K05LV AT40K10LV AT40K20LV AT40K40LV 1.5 1.8 2.0 2.5 ns ns ns ns Rising edge clock Clock Sector Driver t PD (Maximum) colclk -> secclk colclk -> secclk colclk -> secclk colclk -> secclk AT40K05LV AT40K10LV AT40K20LV AT40K40LV 1.0 1.0 1.0 1.0 ns ns ns ns Rising edge clock GSRN Input Buffer tPD (Maximum) pad -> GSRN pad -> GSRN pad -> GSRN pad -> GSRN AT40K05LV AT40K10LV AT40K20LV AT40K40LV 4.5 5.4 6.3 8.2 ns ns ns ns Global Clock to Output tPD (Maximum) clock pad -> out clock pad -> out clock pad -> out clock pad -> out AT40K05LV AT40K10LV AT40K20LV AT40K40LV 13.0 13.4 13.8 14.5 ns ns ns ns Rising edge clock Fully loaded clock tree Rising edge DFF 20 mA output buffer 50 pf pin load Fast Clock to Output t PD (Maximum) clock pad -> out clock pad -> out clock pad -> out clock pad -> out AT40K05LV AT40K10LV AT40K20LV AT40K40LV 12.4 12.7 13.0 13.5 ns ns ns ns Rising edge clock Fully loaded clock tree Rising edge DFF 20 mA output buffer 50 pf pin load |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
