AD9244 datasheet(18/37 Pages) AD

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AD9244

Rev. C | Page 17 of 36

THEORY OF OPERATION

The AD9244 is a high performance, single-supply 14-bit ADC.

In addition to high dynamic range Nyquist sampling, it is

designed for excellent IF undersampling performance with an

analog input as high as 240 MHz.

The AD9244 uses a calibrated 10-stage pipeline architecture

with a patented, wideband, input sample-and-hold amplifier

(SHA) implemented on a cost-effective CMOS process. Each

stage of the pipeline, excluding the last, consists of a low resolu-

tion flash ADC along with a switched capacitor DAC and

interstage residue amplifier (MDAC). The MDAC amplifies the

difference between the reconstructed DAC output and the flash

input for the next stage in the pipeline. One bit of redundancy is

used in each of the stages to facilitate digital correction of flash

errors. The last stage simply consists of a flash ADC.

The pipeline architecture allows a greater throughput rate at the

expense of pipeline delay or latency. While the converter cap-

tures a new input sample every clock cycle, it takes eight clock

cycles for the conversion to be fully processed and appear at the

output, as illustrated in Figure 2. This latency is not a concern

in many applications. The digital output, together with the OTR

indicator, is latched into an output buffer to drive the output

pins. The output drivers of the AD9244 can be configured to

interface with 5 V or 3.3 V logic families.

The AD9244 has a duty clock stabilizer (DCS) that generates its

own internal falling edge to create an internal 50% duty cycle

clock, independent of the externally applied duty cycle. Control

of straight binary or twos complement output format is accom-

plished with the DFS pin.

The ADC samples the analog input on the rising edge of the

clock. While the clock is low, the input SHA is in sample mode.

When the clock transitions to a high logic level, the SHA goes

into the hold mode. System disturbances just prior to or imme-

diately after the rising edge of the clock and/or excessive clock

jitter can cause the SHA to acquire the wrong input value and

should be minimized.

ANALOG INPUT AND REFERENCE OVERVIEW

The differential input span of the AD9244 is equal to the poten-

tial at the VREF pin. The VREF potential can be obtained from

the internal AD9244 reference or an external source.

In differential applications, the center point of the input span is

the common-mode level of the input signals. In single-ended

applications, the center point is the dc potential applied to one

input pin while the signal is applied to the opposite input pin.

Figure 40 to Figure 42 show various system configurations.

REFT

REFB

VREF

SENSE

AD9244

VIN+

VIN–

20pF

μF

0.1

μF

0.1

μF

0.1

μF

0.1

μF

50V

REFGND

2.5V

1.5V

2.5V

1.5V

Figure 40. 2 V p-p Differential Input, Common-Mode Voltage = 2 V

REFT

REFB

VREF

SENSE

AD9244

VIN+

VIN–

20pF

μF

0.1

μF

0.1

μF

0.1

μF

0.1

μF

REFGND

3.0V

2.0V

Figure 41. 2 V p-p Single-Ended Input, Common-Mode Voltage = 2 V

REFT

REFB

VREF

SENSE

AD9244

VIN+

VIN–

20pF

0.1pF

2.5V

μF

0.1

μF

0.1

μF

0.1

μF

0.1

μF

REFGND

3.0V

2.0V

3.0V

2.0V

Figure 42. 2 V p-p Differential Input, Common-Mode Voltage = 2.5 V

Figure 43 is a simplified model of the AD9244 analog input,

showing the relationship between the analog inputs, VIN+,

VIN–, and the reference voltage, VREF. Note that this is only a

symbolic model and that no actual negative voltages exist inside

the AD9244. Similar to the voltages applied to the top and bot-

tom of the resistor ladder in a flash ADC, the value VREF/2

defines the minimum and maximum input voltages to the

ADC core.

AD9244

+VREF/2

–VREF/2

VIN+

VIN–

VCORE

–

ADC

CORE

Figure 43. Equivalent Analog Input of AD9244

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