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AD9244

Rev. C | Page 22 of 36

Out of Range (OTR)

An out-of-range condition exists when the analog input voltage

is beyond the input range of the ADC. OTR is a digital output

that is updated along with the data output corresponding to the

particular sampled input voltage. Thus, OTR has the same pipe-

line latency as the digital data. OTR is low when the analog

input voltage is within the analog input range and high when

the analog input voltage exceeds the input range, as shown in

Figure 52. OTR remains high until the analog input returns to

within the input range and another conversion is completed.

By logically AND’ing OTR with the MSB and its complement,

overrange high or underrange low conditions can be detected.

Table 11 is a truth table for the overrange/underrange circuit in

Figure 53, which uses NAND gates. Systems requiring

programmable gain conditioning of the AD9244 can after eight

clock cycles detect an OTR condition, thus eliminating gain

selection iterations. In addition, OTR can be used for digital

offset and gain calibration.

OTR DATA OUTPUTS

OTR

+FS – 1 LSB

+FS – 1/2 LSB

+FS

–FS

–FS + 1/2 LSB

–FS – 1/2 LSB

1111

1110

0000

0001

0000

Figure 52. OTR Relation to Input Voltage and Output Data

Table 11. Output Data Format

OTR

MSB

Analog Input Is

Within range

Underrange

Overrange

MSB

OTR

MSB

OVER = 1

UNDER = 1

Figure 53. Overrange/Underrange Logic

Digital Output Enable Function (OEB)

The AD9244 has three-state ability. If the OEB pin is low, the

output data drivers are enabled. If the OEB pin is high, the out-

put data drivers are placed in a high impedance state. The

three-state ability is not intended for rapid access to the data

bus. Note that OEB is referenced to the digital supplies

(DRVDD) and should not exceed that supply voltage.

Clock Overview

The AD9244 has a flexible clock interface that accepts either a

single-ended or differential clock. An internal bias voltage

facilitates ac coupling using two external capacitors. To remain

backward compatible with the single-pin clock scheme of the

AD9226, the AD9244 can be operated with a dc-coupled,

single-pin clock by grounding the CLK− pin and driving CLK+.

When the CLK− pin is not grounded, the CLK+ and CLK– pins

function as a differential clock receiver. When CLK+ is greater

than CLK–, the SHA is in hold mode; when CLK+ is less than

CLK–, the SHA is in track mode (see Figure 54 for timing). The

rising edge of the clock (CLK+ – CLK–) switches the SHA from

track to hold, and timing jitter on this transition should be mini-

mized, especially for high frequency analog inputs.

CLK–

CLK+

CLK–

CLK+

SHA IN

HOLD

SHA IN

TRACK

Figure 54. SHA Timing

It is often difficult to maintain a 50% duty cycle to the ADC,

especially when driving the clock with a single-ended or sine

wave input. To ease the constraint of providing an accurate 50%

clock, the ADC has an optional internal duty cycle stabilizer

(DCS) that allows the rising clock edge to pass through with

minimal jitter, and interpolates the falling edge, independent of

the input clock falling edge. The DCS is described in greater

detail in the Clock Stabilizer (DCS) section.

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