S71PL254 datasheet(133/196 Pages) SPANSION

133 / 196 page

April 26, 2004 pSRAM_Type06_14_A0

pSRAM Type 6

133

Advance

I n f o rmatio n

Provisions of Address Skew

Read

In case multiple invalid address cycles shorter than tRC min sustain over 10 µs in

an active status, at least one valid address cycle over tRC min is required during

10µs.

Write

In case multiple invalid address cycles shorter than tWC min sustain over 10 µs in

an active status, at least one valid address cycle over tWC min is required during

10 µs.

Notes:

1. Stresses greater than listed under "Absolute Maximum Ratings" section may cause permanent damage to the device.

2. All voltages are reference to GND.

3. IDDO depends on the cycle time.

4. IDDO depends on output loading. Specified values are defined with the output open condition.

5. AC measurements are assumed tR, tF = 5 ns.

6. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage

reference levels.

7. Data cannot be retained at deep power-down stand-by mode.

8. If OE# is high during the write cycle, the outputs will remain at high impedance.

9. During the output state of I/O signals, input signals of reverse polarity must not be applied.

10. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance.

11. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance.

Figure 56. Read

Figure 57. Write

over 10

µs

tRCmin

CE1#

WE#

Address

tWPmin

tWCmin

CE1#

WE#

Address

S71PL254 Datasheet(PDF) 133 Page - SPANSION