LTM2893 datasheet(12/32 Pages) LINER

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LTM2893/LTM2893-1

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APPLICATIONS INFORMATION

TheSPIbuslacksaformalstandard,andtherefore,various

implementationsofprotocol,bitlengths,andsignalpolari-

ties exist. In the universe of analog-to-digital converters

(ADCs) with serial peripheral interfaces (SPI), a nominal

set of requirements must be met to operate properly with

the LTM2893.

First, the LTM2893 operates similar to mode (0, 0). The

data is captured and shifted on the rising edge of SCK. All

setupandholdtimingcharacteristicsarerelatedtotherising

edge of the SCK. In a normal mode (0, 0) SPI pattern, the

data changes on the falling edge of the SCK. Be aware of

the timing delay for the data to be stable before the rising

edge SCK capture, if the chosen ADC changes data on the

fallingedge.At100MHzand66MHz,theLTM2893changes

MISOA and MISOB after the rising edge in order to allow

for the maximum time for data to change, stabilize, and

be ready for the next rising clock edge.

Second, the SCK and SS must be dedicated to the opera-

tion of reading or writing data. Some ADC interfaces use

the SCK as a conversion clock in addition to the shift clock

function for the SPI port. Excessive SCK transitions will

asserttheFAULTpinasaSPIbufferunder-run.Theisolated

side will transition SCK2 based on the configured count

and will not mimic the extra SCK transitions.

The slave select (SS) is low true and frames the SPI trans-

action. With the LTM2893, if a single ADC is implemented,

thelogicsideSScanbedrivenlowduringnormaloperation

and the isolated side SS2 can be left open. Otherwise, the

SS must be returned to a high, and then can be driven

low to clear the FAULT pin. The LTM2893-1 requires the

SS to frame the SPI transaction.

The CNV to CNV2 signal is initiated on a rising edge. The

falling edge of CNV is ignored. The falling edge of CNV2 is

generated internally and has up to 5ns of jitter. The positive

pulse width of CNV2 is dependent on the configured SCK2

frequency. SCK2 frequencies of 40MHz or greater have

a pulse width of ~40ns, and SCK2 frequencies of 33MHz

or below have a pulse width of ~60ns.

ADCs with or without conversion start or busy pins are

compatible with the LTM2893.

ADCs that offer conversion start signals and busy signals

connect directly to the CNV2 and BUSY2 pins on the

LTM2893. The anticipated operation of a conversion start

signalistoinitiatetheconversionoperationandforthebusy

signal to be high during the conversion. The busy signal

is anticipated to go low when the conversion is complete.

ADCs that offer conversion start signals without a busy

signal are anticipated to allow reading of the prior SPI

resultwhilethecurrentconversionisongoing.Connectthe

CNV2 signal to the ADC conversion start and the BUSY2

signal. This will force the LTM2893 to read data from the

ADC after the CNV2 signal goes low.

ADCs that do not have a conversion start or a busy signal

areanticipatedtoallowreadingofthepriorSPIresultwhile

a conversion is ongoing. Connect the CNV2 signal to the

BUSY2 signal. This will force the LTM2893 to read data

from the ADC after the CNV2 signal goes low. This may

include ADCs that use the CS signal to initiate a conver-

sion start. An example of this is shown in Figure 15 with

an LTC2314-14.

TIMING AND CONTROL

A conversion is initiated by CNV. A rising edge on CNV

will start a conversion and start the process controlling

the BUSY output and the collection of ADC results. Once

a conversion has been initiated, do not start a new conver-

sion until the current process is completed and the ADC

results have been read or else data loss may occur. Once a

CNV rising edge is detected, the BUSY output is asserted

high and remains high throughout the ADC conversion

phase and is de-asserted at the point the most significant

bit is ready to be read. Reading data from the serial digital

interface before the BUSY output is de-asserted will result

in erroneous results and an assertion of the FAULT flag. To

enable the serial digital interface assert the SS input low.

The SS input allows the serial digital interface to be shared

with other devices. When the device count is 1-2, the SS

input may be held low at all times or asserted low at each

read of the ADC results after the BUSY output has gone low.

Asserting SS low at each ADC result read will allow a FAULT

report to be cleared. At each SCK rising edge, the MISOA

and MISOB data is read by the external master controller

and the next data bit is registered to the MISOA and MISOB

pin. The external master controller must read the result in

one transaction prior to the next CNV rising edge.

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