LTM2893 datasheet(23/32 Pages) LINER

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LTM2893/LTM2893-1

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TIMING DIAGRAMS

The SS2 signal is not necessary on all ADC parts. The SS2

signal can be left unconnected if the interfaced ADC does

not require a chip select.

The period of time referenced as tQUIET2 is the acquisition

quiet time allocated to the connected ADC. tQUIET2 is a

minimum of tBUSY2FBUSYF + tQUIET, the additional delay

is added by delaying the next CNV rising edge from the

last rising edge of SS or SCK. tSCK2SSDIS is approximately

1.5/SCK2.

The default SCK2 frequency is 100MHz; configure the

SCK2 frequency to match the requirements of the ADC.

The range of variations in the SCK2 period are detailed

in Table 5. The temperature dependence of the SCK2

Frequency is shown in the typical curves section’s SCK2

Frequency Variation vs Temperature plot. For example,

using the limits from Table 5, an H-grade part configured

for SCK2 = 50MHz may operate from 46.25 to 52.65MHz

over the entire temperature range

ISOLATED INTERFACE WITH READ AND WRITE USING

THE LTM2893-1

The LTM2893-1 isolated side operates ahead of the logic

side when reading data from the ADC. In order to write

data to the ADC a second SPI transaction is initiated after

the full logic side SPI word has been received from MOSI.

The logic side sees one write/read SPI transaction and the

isolatedsideseestwotransactions,areadandthenawrite.

The second SPI transaction on the isolated side incurs a

time penalty and requires flexibility on the part of the ADC.

Figure 11 demonstrates the signal patterns that the ADC

will see when written. The first SPI transaction reads the

ADC results on MISOA2 and MISOB2 while MOSI2 is ‘0’

and then clears the SS2 signal. A second SPI transaction

occurs, after the write data is received, in which the MOSI2

data is written to the ADC. The ADC cycle time must be

extendedbythemastercontrollingdevicetoaccommodate

the additional SPI write.

To calculate the time to the next CNV rising edge for the

LTM2893-1:

Figure 10. Isolated Side Interface for an ADC Conversion

CNV2

BUSY2

ADC CONVERSION TIMING DIAGRAM ISOLATED SIDE INTERFACE

SS2

SCK2

MISOA2

DI17

ADC CONVERSION TIME (tCNVADC)

DI0

ADC CYCLE TIME

ADC ACQUISITION TIME

DI17

DI0

MISOB2

2893 F10

tCNV2H

tCNV2toADCstart

tBUSY2FSS2F

tSS2FSCK2

tSCK2

tSCK2H

tSCK2L

tSCK2SSDIS

tQUIET2

tHDMISO2

tSUMISO2

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