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LTM2893 Datasheet(PDF) 26 Page - Linear Technology |
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LTM2893 Datasheet(HTML) 26 Page - Linear Technology |
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26 / 32 page ![]() LTM2893/LTM2893-1 26 28931fb For more information www.linear.com/LTM2893 TYPICAL APPLICATIONS Figure 15. Isolated 2Msps LTC2314-14 0V to 4.096V Input Range, ADC Without a CNV or BUSY, LTC2314 CS Is Synchronized to Low Jitter CNV2 LTM2893 100k VL VCC VL2 VCC2 CSC CNV BUSY SS SCK MISOA MISOB CNV2 BUSY2 BUSYS SS2 SCK2 MISOA2 MISOB2 VDD 5Vi 5V 3.3V REF OVDD IN+ 2.2µF 2.2µF 2.2µF LTC2314-14 CNV2 5Vi 5Vi CONFIGURATION REGISTERS WRITE 0x20h AND 0x83h SETS SCK2 TO 50MHz AND WORDLENGTH TO 16-BIT. NOTE: THE LTC2314-14 CHANGES SDO ON THE FALLING EDGE OF SCK, WITH A MAXIMUM DELAY UNTIL THE DATA IS VALID OF 9.1ns. THE SCK2 FREQUENCY IS REDUCED TO 50MHz IN THIS APPLICATION TO GUARANTEE SETUP TIME. MASTER FPGA OR MICROPROCESSOR (HOST) 28931 F15 SCK SDO 22nF 50 0V TO 4.096V INPUT BUSY CNV CNV2 = BUSY2 SS2 SCK2 (50MHz) tCNV2H MISOA2 ADC RESULT (ISOLATED SIDE) SS SCK (50MHz) MISOA ADC RESULT (LOGIC SIDE) 500ns CS PRE CLR D CLK NC7SZ74 CNV2 74VHC04 Q |
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