LTM2893 datasheet(17/32 Pages) LINER

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LTM2893/LTM2893-1

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Figure 3. LTM2893-1 Example Word Delay on Isolated

Transactions When Logic Side Reads and Writes After

BUSY Falls

Figure 4. LTM2893-1 Example Word Delay on Isolated

Transactions When Logic Side Reads and Writes After a

Delay and with a Slower SCK

Figure 5. LTM2893-1 Worst Case Example Word Delay

on Isolated Transactions When Logic Side Reads and

Writes After a Long Delay

APPLICATIONS INFORMATION

to a CNV rising edge, an ADC command may be written to

the LTM2893 and it is transferred to the ADC. On all future

transactions,theisolatedsidewillcommunicatetotheADC

through a two-step process. The ADC is read, in the first

cycle, when data is ready, indicated by the ADC’s BUSY

signal into BUSY2. Then the ADC is written on a second

cycle after write data is received from the logic side. See

Figure 11 for a timing representation of the transactions.

The writing of data to the ADC will begin after a full

word is received from the master and at the next avail-

able isolated side word boundary. Due to a built-in

delay across the isolation barrier, the writing of a word

is forced to the next available time slot. Examples of

the overall delay that can occur are shown in Figure 3,

Figure 4, and Figure 5. Delay between conversion starts

must be added to account for the write delays. Not all

ADCs will accept the second SPI transaction and may not

operate as expected.

ISOLATED TRANSACTIONS

LOGIC TRANSACTIONS

CNV

BUSY

MOSI2

MISOx2

MOSI

MISOx

RDx = READING DATA WORD, WDx = WRITTING DATA WORD

2893 F03

tCYCLETIME

RD1

RD2

RD3

RD4

RD3

WD1

WD2

WD3

WD4

WD3

WD2

WD1

WDx WRITTEN ON NEXT

AVAILABLE WORD BOUNDARY

tADDISODELAY

TIME FOR LOGIC SIDE SPI TRANSACTION

CNV

BUSY

MOSI2

MISOx2

MOSI

MISOx

RDx = READING DATA WORD, WDx = WRITTING DATA WORD

2893 F04

tCYCLETIME

RD1

RD2

RD2 RD3 RD4

RD4

RD3

WD1

WD2

WD3

WD4

WD3

WD2

WD1

WDx WRITTEN ON NEXT

AVAILABLE WORD BOUNDARY

tADDISODELAY

TIME FOR LOGIC SIDE SPI TRANSACTION

ISOLATED TRANSACTIONS

LOGIC TRANSACTIONS

CNV

BUSY

MOSI2

MISOx2

MOSI

MISOx

RDx = READING DATA WORD, WDx = WRITTING DATA WORD

2893 F05

tCYCLETIME

RD1 RD2 RD3 RD4

WD4

WD3

WD2

WDx WRITTEN ON NEXT

AVAILABLE WORD BOUNDARY

tADDISODELAY

TIME FOR LOGIC SIDE SPI TRANSACTION

WD1

RD1

WD1 WD2 WD3 WD4

RD2 RD3

RD4

DELAY FROM

BUSY FALL

ISOLATED TRANSACTIONS

LOGICTRANSACTIONS

ADDITIONAL ADC CONFIGURATIONS

To interface ADCs without a BUSY signal and to allow

immediate reading, including the LTC2314-14, connect

CNV2 to BUSY2 and connect BUSYS to GND2. This

configuration will read the ADC SPI port shortly after

the CNV2 signal goes low, maximizing data rate. In this

configuration, a sampling rate of 2Msps can be achieved

with the LTC2314-14, see Figure 15. The sampling rate

is constrained by the data changing on the falling edge

of SCK and the delay for the data to be valid is as much

as 9.1ns (per the LTC2314-14 data sheet). To guarantee

setup time SCK2 frequency is set to 50MHz.

PARALLEL CONNECTING ADCs

MISOA and MISOB pins allow two data words to be read

simultaneously. Connect pairs of ADC SDO outputs to

the isolated side MISOA2 and MISOB2 inputs. The pairs

of ADCs are read simultaneously with the SCK2 signal.

OR the BUSY outputs of the ADCs so the last ADC ready

initiates the reading of the results. If one pair of ADCs is

connected, the BUSY2 and BUSYS inputs accomplish the

OR function. If additional ADCs are connected, an external

OR is necessary.

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