AM3351 datasheet(213/252 Pages) TI1

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

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SPRS717J – OCTOBER 2011 – REVISED APRIL 2016

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Peripheral Information and Timings

7.12 Multichannel Serial Port Interface (McSPI)

For more information, see the Multichannel Serial Port Interface (McSPI) section of the AM335x and

AMIC110 Sitara Processors Technical Reference Manual.

7.12.1 McSPI Electrical Data and Timing

The following timings are applicable to the different configurations of McSPI in master or slave mode for

any McSPI and any channel (n).

7.12.1.1 McSPI—Slave Mode

Table 7-80. McSPI Timing Conditions – Slave Mode

PARAMETER

MIN

MAX

UNIT

Input Conditions

Input signal rise time

Input signal fall time

Output Condition

Cload

Output load capacitance

Table 7-81. Timing Requirements for McSPI Input Timings—Slave Mode

(see Figure 7-88)

NO.

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

tc(SPICLK)

Cycle time, SPI_CLK

62.5

124.8

tw(SPICLKL)

Typical pulse duration, SPI_CLK low

0.5P –

3.12(1)

0.5P +

3.12(1)

0.5P –

3.12(1)

0.5P +

3.12(1)

tw(SPICLKH)

Typical pulse duration, SPI_CLK high

0.5P –

3.12(1)

0.5P +

3.12(1)

0.5P –

3.12(1)

0.5P +

3.12(1)

tsu(SIMO-SPICLK)

Setup time, SPI_D[x] (SIMO) valid before SPI_CLK

active edge(2)(3)

12.92

th(SPICLK-SIMO)

Hold time, SPI_D[x] (SIMO) valid after SPI_CLK

active edge(2)(3)

12.92

tsu(CS-SPICLK)

Setup time, SPI_CS valid before SPI_CLK first

edge(2)

12.92

th(SPICLK-CS)

Hold time, SPI_CS valid after SPI_CLK last edge(2)

12.92

(1) P = SPI_CLK period.

(2) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and

capture input data.

(3) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.

Table 7-82. Switching Characteristics for McSPI Output Timings—Slave Mode

(see Figure 7-89)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

td(SPICLK-SOMI)

Delay time, SPI_CLK active edge to

SPI_D[x] (SOMI) transition(1)(2)

–4.00

17.12

–4.00

17.12

td(CS-SOMI)

Delay time, SPI_CS active edge to

SPI_D[x] (SOMI) transition(1)(2)

17.12

(1) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and

capture input data.

(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.

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