AM3351 datasheet(216/252 Pages) TI1

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216

AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

SPRS717J – OCTOBER 2011 – REVISED APRIL 2016

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Peripheral Information and Timings

7.12.1.2 McSPI—Master Mode

Table 7-83. McSPI Timing Conditions – Master Mode

PARAMETER

LOW LOAD

HIGH LOAD

UNIT

MIN

MAX

MIN

MAX

Input Conditions

Input signal rise time

Input signal fall time

Output Condition

Cload

Output load capacitance

Table 7-84. Timing Requirements for McSPI Input Timings – Master Mode

(see Figure 7-90)

NO.

OPP100

OPP50

UNIT

LOW LOAD

HIGH LOAD

LOW LOAD

HIGH LOAD

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

tsu(SOMI-

SPICLKH)

Setup time, SPI_D[x] (SOMI) valid before

SPI_CLK active edge(1)

2.29

3.02

2.29

3.02

th(SPICLKH-

SOMI)

Hold time, SPI_D[x]

(SOMI) valid after

SPI_CLK active edge(1)

Industrial extended

temperature

(-40°C to 125°C)

7.1

All other

temperature ranges

4.7

(1) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.

Table 7-85. Switching Characteristics for McSPI Output Timings – Master Mode

(see Figure 7-91)

NO.

PARAMETER

OPP100

OPP50

UNIT

LOW LOAD

HIGH LOAD

LOW LOAD

HIGH LOAD

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

tc(SPICLK)

Cycle time, SPI_CLK

20.8

41.6

tw(SPICLKL)

Typical pulse duration,

SPI_CLK low

0.5P –

1.04(1)

0.5P +

1.04(1)

0.5P –

2.08(1)

0.5P +

2.08(1)

0.5P –

1.04(1)

0.5P +

1.04(1)

0.5P –

2.08(1)

0.5P +

2.08(1)

tw(SPICLKH)

Typical pulse duration,

SPI_CLK high

0.5P –

1.04(1)

0.5P +

1.04(1)

0.5P –

2.08(1)

0.5P +

2.08(1)

0.5P –

1.04(1)

0.5P +

1.04(1)

0.5P –

2.08(1)

0.5P +

2.08(1)

tr(SPICLK)

Rising time, SPI_CLK

3.82

tf(SPICLK)

Falling time, SPI_CLK

3.44

td(SPICLK-SIMO)

Delay time, SPI_CLK

active edge to SPI_D[x]

(SIMO) transition(2)

–3.57

3.57

–4.62

4.62

–3.57

3.57

–4.62

4.62

td(CS-SIMO)

Delay time, SPI_CS active

edge to SPI_D[x] (SIMO)

transition(2)

3.57

4.62

3.57

4.62

td(CS-SPICLK)

Delay time,

SPI_CS active

to SPI_CLK

first edge

Mode 1

and 3(3)

A – 4.2(4)

A – 2.54(4)

A – 4.2(4)

A – 2.54(4)

Mode 0

and 2(3)

B – 4.2(5)

B – 2.54(5)

B – 4.2(5)

B – 2.54(5)

td(SPICLK-CS)

Delay time,

SPI_CLK last

edge to

SPI_CS

inactive

Mode 1

and 3(3)

B – 4.2(5)

B – 2.54(5)

B – 4.2(5)

B – 2.54(5)

Mode 0

and 2(3)

A – 4.2(4)

A – 2.54(4)

A – 4.2(4)

A – 2.54(4)

(1) P = SPI_CLK period.

(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.

(3) The polarity of SPIx_CLK and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all

software configurable:

–

SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).

–

SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).

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