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80C286 Datasheet(PDF) 48 Page - Renesas Technology Corp |
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80C286 Datasheet(HTML) 48 Page - Renesas Technology Corp |
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48 / 65 page ![]() FN2947 Rev.3.00 Page 48 of 65 January 28, 2008 80C286 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2003-2008. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. FIGURE 37. EXITING AND ENTERING HOLD NOTES: 48. These signals may not be driven by the 80C286 during the time shown. The worst case in terms of latest float time is shown. 49. The data bus will be driven as shown if the cycle before TI in the diagram was a write TC. 50. The 80C286 puts its status pins in a high impedance logic one state during TH. 51. For HOLD request set up to HLDA, refer to Figure 29. 52. BHE and LOCK are driven at this time but will not become valid until TS. 53. The data bus will remain in a high impedance state if a read cycle is performed. Waveforms (Continued) TH 1 BUS CYCLE TYPE VCH CLK VCL S1 S0 BHE, LOCK 2 HLDA CLK D15 - D0 PCLK A23 - A0, M/IO, COD/INTA 1 2 1 2 1 2 16 16 15 15 15 15 14 13 12A 12B TS OR TI TI TH (SEE NOTE 51) (SEE NOTE 50) (SEE NOTE 48) (SEE NOTE 49) (SEE NOTE 53) (SEE NOTE 52) (SEE NOTE 50) IF TS IF NPX TRANSFER VALID VALID IF WRITE |
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