80C286 datasheet(17/65 Pages) RENESAS

17 / 65 page

80C286

FN2947 Rev.3.00

Page 17 of 65

January 28, 2008

the tables in memory. The 16-bit offset is added to the seg-

ment base address to form the physical address as shown in

Figure 8. The tables are automatically referenced by the CPU

whenever a segment register is loaded with a selector. All

80C286 instructions which load a segment register will refer-

ence the memory based tables without additional software.

The memory based tables contain 8 byte values called

descriptors.

Descriptors

Descriptors define the use of memory. Special types of

descriptors also define new functions for transfer of control and

task switching. The 80C286 has segment descriptors for code,

stack and data segments, and system control descriptors for

special system data segments and control transfer operations.

Descriptor accesses are performed as locked bus operations

to assure descriptor integrity in multi-processor systems.

Code and Data Segment Descriptors (S = 1)

Besides segment base addresses, code and data descriptors

contain other segment attributes including segment size (1 to 64K

bytes), access rights (read only, read/write, execute only, and

execute/read), and presence in memory (for virtual memory sys-

tems) (See Table 10). Any segment usage violating a segment

attribute indicated by the segment descriptor will prevent the

memory cycle and cause an exception or interrupt.

Code and data (including stack data) are stored in two types of

segments: code segments and data segments. Both types are

identified and defined by segment descriptors (S = 1). Code

segments are identified by the executable (E) bit set to 1 in the

descriptor access rights byte. The access rights byte of both

code and data segment descriptor types have three fields in

common: present (P) bit, Descriptor Privilege Level (DPL), and

accessed (A) bit. If P = 0, any attempted use of this segment

will cause a not-present exception. DPL specifies the privilege

level of the segment descriptor. DPL controls when the

descriptor may be used by a task (refer to privilege discussion

below). The A bit shows whether the segment has been previ-

ously accessed for usage profiling, a necessity for virtual mem-

ory systems. The CPU will always set this bit when accessing

the descriptor.

RESERVED †

ACCESS

RIGHTS BYTE

PDPL STYPE A

BASE 23 - 16

BASE 15 - 0

LIMIT 15 - 0

70 7

† MUST BE SET TO 0 FOR COMPATIBILITY WITH FUTURE UPGRADES

FIGURE 9. CODE OR DATA SEGMENT DESCRIPTOR

TABLE 10. CODE AND DATA SEGMENT DESCRIPTOR FORMATS - ACCESS RIGHTS BYTE DEFINITION

BIT

POSITION

NAME

FUNCTION

Present (P)

P = 1

Segment is mapped into physical memory.

P = 0

No mapping to physical memory exits, base and limit are not used.

6 - 5

Descriptor Privilege

Level (DPL)

Segment privilege attribute used in privilege tests.

Segment Descriptor (S) S = 1

Code or Data (includes stacks) segment descriptor

S = 0

System Segment Descriptor or Gate Descriptor

Executable (E)

E = 0

Data segment descriptor type is:

If Data Segment

(S = 1, E = 0)

Expansion Direction

(ED)

ED = 0

Expand up segment, offsets must be

 limit.

ED = 1

Expand down segment, offsets must be > limit.

Writable (W)

W = 0

Data segment may not be written into.

W = 1

Data segment may be written into.

Type

Field

Definition

Executable (E)

E = 1

Code Segment Descriptor type is:

If Code Segment

(S = 1, E = 1)

Conforming (C)

C = 1

Code segment may only be executed when CPL



DPL and CPL remains unchanged.

Readable (R)

R = 0

Code segment may not be read.

R = 1

Code segment may be read.

Accessed (A)

A = 0

Segment has not been accessed.

A = 1

Segment selector has been loaded into segment register or used by selector

test instructions.

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