80C286 datasheet(65/65 Pages) RENESAS

65 / 65 page

80C286

FN2947 Rev.3.00

Page 65 of 65

January 28, 2008

where:

Footnotes

The Effective Address (EA) of the memory operand is com-

puted according to the mod and r/m fields:

if mod = 11 then r/m is treated as a REG field

if mod = 00 then DISP = 0†, disp-low and disp-high are absent

if mod = 01 then DISP = disp-low sign extended to 16 bits,

disp-high is absent

if mod = 10 then DISP = disp-high: disp-low

if r/m = 000 then EA = (BX) + (SI) + DISP

if r/m = 001 then EA = (BX) + (DI) + DISP

if r/m = 010 then EA = (BP) + (SI) + DISP

if r/m = 011 then EA = (BP) + (DI) + DISP

if r/m = 100 then EA = (SI) + DISP

if r/m = 101 then EA = (DI) + DISP

if r/m = 110 then EA + (BP) + DISP (Note 60)

if r/m = 111 then EA = (BX) + DISP

DISP follows 2nd byte of instruction (before data is required)

NOTE:

59. Except if mod = 00 and r/m = 110 then EQ = disp-high: disp-low.

Segment Override Prefix

reg is assigned according to the following:

REG is assigned according to the following table:

The physical addresses of all operands addressed by the BP reg-

ister are computed using the SS segment register. The physical

addresses of the destination operands of the string primitive oper-

ations (those addressed by the DI register) are computed using

the ES segment, which may not be overridden.

80C286 Machine Instruction Encoding Matrix (Continued)

mod r/mm

000

001

010

011

100

101

110

111

Immed

ADD

ADC

SBB

AND

SUB

XOR

CMP

Shift

ROL

ROR

RCL

RCR

SHL/SAL

SHR

SAR

Grp 1

TEST

NOT

NEG

MUL

IMUL

DIV

IDIV

Grp 2

INC

DEC

CALL

l, id

JMP

l, id

PUSH

PVAM 0

SLDT

STR

LLDT

LTR

VERR

VERW

PVAM 1

SGDT

SIDT

LGDT

LIDT

SMSW

LMSW

PVAM 2

LAR

PVAM 3

LSL

PVAM 6

CLTS

b = byte operation

d = direct

= from CPU reg

= immediate

ia = immediate to AX

id = indirect

is = immediate byte sign extension

= long i.e., intersegment

n = 2nd byte of PVAM instruction

m = memory

r/m = EA is second byte

= short intrasegment

sr = segment register

= to CPU register

= variable

= word operation

z= zero

001

reg

110

REG

SEGMENT REGISTER

16-BIT (w = 1)

8-BIT (w = 0)

000

001

010

011

100

101

110

111

80C286 Datasheet(PDF) 65 Page - Renesas Technology Corp

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