80C286 datasheet(24/65 Pages) RENESAS

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80C286

FN2947 Rev.3.00

Page 24 of 65

January 28, 2008

function of the IRET instruction. If NT = 0, the IRET instruction

performs the regular current task by popping values off the

stack; when NT = 1, IRET performs a task switch operation

back to the previous task.

When a CALL, JMP, or INT instruction initiates a task switch,

the old (except for case of JMP) and new TSS will be marked

busy and the back link field of the new TSS set to the old TSS

selector. The NT bit of the new task is set by CALL or INT initi-

ated task switches. An interrupt that does not cause a task

switch will clear NT. NT may also be set or cleared by POPF or

IRET instructions.

The task state segment is marked busy by changing the

descriptor type field from Type 1 to Type 3. Use of a selector

that references a busy task state segment causes Exception

13.

Processor Extension Context Switching

The context of a processor extension is not changed by the task

switch operation. A processor extension context need only be

changed when a different task attempts to use the processor

extension (which still contains the context of a previous task).

The 80C286 detects the first use of a processor extension after

a task switch by causing the processor extension not present

exception (7). The interrupt handler may then decide whether a

context change is necessary.

Whenever the 80C286 switches tasks, it sets the Task

Switched (TS) bit of the MSW. TS indicates that a processor

extension context may belong to a different task than the cur-

rent one. The processor extension not present exception (7)

will occur when attempting to execute an ESC or WAIT

instruction if TS = 1 and a processor extension is present (MP

= 1 in MSW).

Pointer Testing Instructions

The 80C286 provides several instructions to speed pointer test-

ing and consistency checks for maintaining system integrity (see

Table 18). These instructions use the memory management

hardware to verify that a selector value refers to an appropriate

segment without risking an exception. A condition flag (ZF) indi-

cates whether use of the selector or segment will cause an

exception.

Double Fault and Shutdown

If two separate exceptions are detected during a single instruc-

tion execution, the 80C286 performs the double fault exception

(8). If an exception occurs during processing of the double fault

exception, the 80C286 will enter shutdown. During shutdown

no further instructions or exceptions are processed. Either NMI

(CPU remains in protected mode) or RESET (CPU exits pro-

tected mode) can force the 80C286 out of shutdown. Shut-

down is externally signalled via a HALT bus operation with A1

LOW.

Protected Mode lnitialization

The 80C286 initially executes in real address mode after

RESET. To allow initialization code to be placed at the top of

physical memory. A23-20 will be HIGH when the 80C286 per-

forms memory references relative to the CS register until CS is

changed. A23-20 will be zero for references to the DS, ES, or

SS segments. Changing CS in real address mode will force

A23-20 LOW whenever CS is used again. The initial CS:lP

value of F000:FFF0 provides 64K bytes of code space for ini-

tialization code without changing CS.

Protected mode operation requires several registers to be ini-

tialized. The GDT and IDT base registers must refer to a valid

GDT and IDT. After executing the LMSW instruction to set PE,

the 80C286 must immediately execute an intrasegment JMP

instruction to clear the instruction queue of instructions

decoded in real address mode.

To force the 80C286 CPU registers to match the initial pro-

tected mode state assumed by software, execute a JMP

instruction with a selector referring to the initial TSS used in the

system. This will load the task register, local descriptor table

The TR should point at a valid TSS since any task switch oper-

ation involves saving the current task state.

TABLE 18. 80C286 POINTER TEST INSTRUCTIONS

INSTRUCTION

OPERANDS

FUNCTION

ARPL

Selector,

Adjust Requested Privilege Level: adjusts the RPL of the selector to the numeric maximum of

current selector RPL value and the RPL value in the register. Set zero flag if selector RPL was

changed by ARPL.

VERR

Selector

VERify for Read: sets the zero flag if the segment referred to by the selector can be read.

VERW

Selector

VERify for Write: sets the zero flag if the segment referred to by the selector can be written.

LSL

Selector

Load Segment Limit: reads the segment limit into the register if privilege rules and descriptor type

allow. Set zero flag if successful.

LAR

Selector

Load Access Rights: reads the descriptor access rights byte into the register if privilege rules al-

low. Set zero flag if successful.

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