80C286 datasheet(28/65 Pages) RENESAS

28 / 65 page

80C286

FN2947 Rev.3.00

Page 28 of 65

January 28, 2008

setup time to system bus command active for any bus opera-

tion by delaying when the system bus command becomes

active. Command delay is controlled by the 82C288 CMDLY

input. After TS, the bus controller samples CMDLY at each fail-

ing edge of CLK. If CMDLY is HIGH, the 82C288 will not acti-

vate the command signal. When CMDLY is LOW, the 82C288

will activate the command signal. After the command becomes

active, the CMDLY input is not sampled.

When a command is delayed, the available response time from

command active to return read data or accept write data is

less. To customize system bus timing, an address decoder can

determine which bus operations require delaying the com-

mand. The CMDLY input does not affect the timing of ALE,

DEN or DT/R.

Figure 23 illustrates four uses of CMDLY. Example 1 shows

delaying the read command two system CLKs for cycle N-1

and no delay for cycle N, and example 2 shows delaying the

read command one system CLK for cycle N-1 and one system

CLK delay for cycle N.

FIGURE 22. BASIC BUS CYCLE

READ BUS CYCLE N

CLK

PROC

A23 - A0

 S1

READY

D15 - D0

READ BUS CYCLE N + 1

1

2

1

2

1

2

1

2

VALID READ

DATA (N)

VALID READ

DATA (N + 1)

VALID ADDR (N)

VALID ADDR (N + 1)

2 PCLK CYCLE TRANSFER

2.5 CLOCK CYCLE ADDRESS TO DATA VALID

2 PCLK CYCLE TRANSFER

CLK

PIPELINING: VALID ADDRESS (N + 1) AVAILABLE IN LAST PHASE OF BUS CYCLE (N).

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