80C286 datasheet(20/65 Pages) RENESAS

20 / 65 page

80C286

FN2947 Rev.3.00

Page 20 of 65

January 28, 2008

The LGDT and LLDT instructions load the base and limit of the

global and local descriptor tables. LGDT and LLDT are privi-

leged, i.e. they may only be executed by trusted programs

operating at level 0. The LGDT instruction loads a six byte field

containing the 16-bit table limit and 24-bit physical base

address of the Global Descriptor Table as shown in Figure 15.

The LDT instruction loads a selector which refers to a Local

Descriptor Table descriptor containing the base address and

limit for an LDT, as shown in Table 11.

Interrupt Descriptor Table

The protected mode 80C286 has a third descriptor table,

called the Interrupt Descriptor Table (IDT) (see Figure 16),

used to define up to 256 interrupts. It may contain only task

gates, interrupt gates and trap gates. The IDT (Interrupt

Descriptor Table) has a 24-bit physical base and 16-bit limit

registers with a six byte value of identical form to that of the

LGDT instruction (see Figure 16 and Protected Mode lnitializa-

tion).

References to IDT entries are made via INT instructions, external

interrupt vectors, or exceptions. The IDT must be at least 256

bytes in size to allocate space for all reserved interrupts.

Privilege

The 80C286 has a four-level hierarchical privilege system

which controls the use of privileged instructions and access to

descriptors (and their associated segments) within a task.

Four-level privilege, as shown in Figure 17, is an extension of

the users/supervisor mode commonly found in minicomputers.

The privilege levels are numbered 0 through 3. Level 0 is the

most privileged level. Privilege levels provide protection within

a task. (Tasks are isolated by providing private LDT’s for each

task.) Operating system routines, interrupt handlers, and other

system software can be included and protected within the vir-

tual address space of each task using the four levels of privi-

lege. Each task in the system has a separate stack for each of

its privilege levels.

Tasks, descriptors, and selectors have a privilege level attri-

bute that determines whether the descriptor may be used.

Task privilege affects the use of instructions and descriptors.

Descriptor and selector privilege only affect access to the

descriptor.

CPU

GDT LIMIT

GDT BASE

24-BIT PHYS AD

LDT

DESCR

SELECTOR

LDT LIMIT

LDT BASE

24-BIT PHYS AD

PROGRAM INVISIBLE

(AUTOMATICALLY

LOADED

FROM LDT DESCR

WITHIN GDT)

GDT

CURRENT

LDT

MEMORY

LDT1

LDTn

FIGURE 14. LOCAL AND GLOBAL DESCRIPTOR TABLE

DEFINITION

RESERVED †

BASE 15 - 0

LIMIT 15 - 0

70 7

† MUST BE SET TO 0 FOR COMPATIBILITY WITH FUTURE UPGRADES

BASE 23 - 16

FIGURE 15. GLOBAL DESCRIPTOR TABLE AND INTERRUPT

DESCRlPTOR TABLE DATA TYPE

IDT LIMIT

IDT BASE

INTERRUPT

DESCRIPTOR

TABLE

MEMORY

GATE FOR

INTERRUPT #n

CPU

GATE FOR

INTERRUPT #1

GATE FOR

INTERRUPT #n-1

GATE FOR

INTERRUPT #0

(IDT)

FIGURE 16. INTERRUPT DESCRIPTOR TABLE DEFINITION

APPLICATIONS

OS EXTENSIONS

SYSTEM

SERVICES

KERNAL

PL = 0

MOST

PRIVILEGED

CPU

ENFORCED

SOFTWARE

INTERFACES

HIGH SPEED

OPERATING

SYSTEM

INTERFACE

PL = 1

PL = 2

PL = 3

NOTE: PL becomes numerically lower as privilege level increases.

FIGURE 17. HIERARCHICAL PRIVILEGE LEVELS

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