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AD9543

Data Sheet

Rev. 0 | Page 34 of 66

PRESCALE DIVIDER

The system clock PLL includes an input prescale divider

programmable for divide ratios of 1 (default), 2, 4, or 8. The

purpose of the divider is to provide flexible frequency planning

for mitigating potential spurs in the output clock signals of

the AD9543. The user selects the divide ratio via the 2-bit

SYSCLK input divider ratio bit field in Register 0x0201. The

corresponding divide value is 2J, where J is the decimal value

of the 2-bit number in the SYSCLK input divider ratio bit field.

For example, given that the SYSCLK input divider ratio bit field is

10 (binary), J = 2 (decimal), yielding a divide ratio of 2J = 22 = 4.

FEEDBACK DIVIDER

The output of the system clock PLL constitutes the system clock

frequency, fS. The system clock frequency depends on the value

of the feedback divider. The feedback divide ratio has a range of

4 to 255, which the user programs via the 8-bit feedback divider

ratio register (the register value is the divide ratio). For example,

a programmed value of 100 (0x64 hexadecimal) yields a divide

ratio of 100.

SYSTEM CLOCK PLL OUTPUT FREQUENCY

Calculate the system clock frequency as follows:

fS = fSYSIN × (K/J)

where:

fSYSIN is the input frequency.

K is the feedback divide ratio.

J is the input divide ratio. J = ½ when using the 2× frequency

multiplier.

The user must choose fSYSIN, K, and J such that fS satisfies the

VCO range of 2250 MHz to 2415 MHz.

SYSTEM CLOCK PLL LOCK DETECTOR

The system clock PLL features a simple lock detector that

compares the time difference between the reference and

feedback clock edges. The user can check the status of the lock

detector via the SYSCLK locked bit in the status readback

registers (Address 0x3000 to Address 0x300A) of the register

map, where Logic 1 indicates locked and Logic 0 unlocked. The

most common reason the system clock PLL fails to lock is due

to the user employing the 2× frequency multiplier with a

reference input clock that deviates from the 50% duty cycle.

SYSTEM CLOCK STABILITY TIMER

Because time processing blocks within the AD9543 depend on

the system clock generating a stable frequency, the system clock

PLL provides an indication of its status. The status of the system

clock PLL is available to the user as well as directly to certain

internal time keeping blocks.

At initial power-up, the system clock status is unknown and

reported as being unstable. However, after the user programs

the system clock registers and the system clock PLL VCO

calibrates, the system clock PLL locks shortly thereafter.

SYSTEM CLOCK INPUT TERMINATION

RECOMMENDATIONS

To connect a crystal resonator to the system clock PLL XOA

and XOB inputs, refer to Figure 23. Be sure to program the

enable maintaining amplifier bit = 1 to select the crystal path.

The 15 pF shunt capacitors shown relate to the CLOAD and CSTRAY

associated with the crystal as follows:

CSHUNT = 2 × (CLOAD – CSTRAY)

For CLOAD = 10 pF and CSTRAY = 2 pF to 5 pF, the value of CSHUNT

is approximately 15 pF.

To connect a TCXO or OCXO with a 3.3 V output, refer to

Figure 24. Be sure to program the enable maintaining amplifier

bit = 0 to select the direct path.

AD9543 Datasheet(PDF) 34 Page - Analog Devices

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