AD9543 datasheet(38/66 Pages) AD

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AD9543

Data Sheet

Rev. 0 | Page 38 of 66

IEEE 1588 SERVO

In this application (shown in Figure 43), the AD9543 provides

all of the jitter cleaning, phase shifting, and synchronization to

an IEEE 1588 servo and software stack in a Telecom-BC (T-BC)

with hybrid support application. This system is also able to act

as an IEEE 1588 master and slave clock.

The PLL0 of the AD9543 provides a filtered, 125 MHz, SyncE

clock.

The PLL1 of the AD9543 provides a 1 pps to 500 MHz output

clock with high resolution output phase adjustment and slew

rate limiting capability. This allows, for example, a GPS signal to

be filtered and, with appropriate PTP software support, provide

PTP asymmetry correction.

The performance and feature set of the AD9543 make it ideal to

enable the latest IEEE 1588 features, as well as the latest ITU-T

packet synchronization related standards for 4G and 5G wireless

networks.

SERIAL CONTROL/STATUS INTERFACE

CLOCK INTERFACES

AD9543

REF_IN1

1REF_IN IS AN OPTIONAL EXTERNAL MASTER CLOCK REFERENCE.

(2kHz to 750MHz)

CLOCK OUT

(1PPS TO 500MHz

WITH OPTIONAL 1PPS

MODULATION)

TIME OF DAY

IN/OUT

(1PPS +

tUART WITH

NEMA FORMAT)

DIGITAL/

ANALOG

PLL0

(WB)

TIME

DAY

PACKET

CLASSIFIER

AND

TIMESTAMP

MAC

CPU

MEMORY

DIGITAL/

ANALOG

PLL1

(WB)

A/B

C/D

125MHz

(FILTERED/ADJUSTED)

125MHz

(FILTERED/ADJUSTED)

ToD IN

ToD OUT

Mgmt

I/F

125MHz

(SyncE/CDR)

1PPS

SERVO CONTROL

SPI/I2C

PORT

RGMII/SGMII

(WITH SyncE SUPPORT)

Figure 43. Using an AD9543 in an IEEE 1588 Version 2 Application

AD9543 Datasheet(PDF) 38 Page - Analog Devices

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