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AD9543

Data Sheet

Rev. 0 | Page 12 of 66

HOLDOVER SPECIFICATIONS

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

HOLDOVER SPECIFICATIONS

Initial Frequency Accuracy

±0.01

±0.1

ppb

AD9543 is configured using Configuration 1 from

Table 22; excludes frequency drift of system clock

(SYSCLK) source; excludes frequency drift of input

reference prior to entering holdover; 160 ms

history timer; history holdoff setting of 8; three

holdover history features (bits) are enabled: delay

history until frequency lock bit, delay history until

phase lock bit, and delay holdover history

accumulation until not phase slew limited bit

Relative Frequency Accuracy Between Channels

Cascaded Operation

ppb

History Averaging Window

0.001

268435

sec

ANALOG PLL (APLL0, APLL1) SPECIFICATIONS

Table 13.

Parameter

Min

Typ

Max

Unit

VCO FREQUENCY RANGE

Analog PLL0 (APLL0)

2424

3232

MHz

Analog PLL1 (APLL1)

3232

4040

MHz

PHASE FREQUENCY DETECTOR (PFD) INPUT FREQUENCY RANGE

162

350

MHz

LOOP BANDWIDTH

260

kHz

PHASE MARGIN

Degrees

OUTPUT CHANNEL DIVIDER SPECIFICATIONS

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT PHASE ADJUST STEP SIZE

tVCO

tVCO = 1/(APLLx VCO frequency), where x = 0, 1

MODULATOR

Carrier Frequency

fVCO ÷ 16

The maximum value is the APLL VCO frequency divided

by 16

Time Deviation (from Nominal

Duty Cycle of Carrier Clock)

216 − 1

tVCO

tVCO = 1/(APLLx VCO frequency), where x = 0, 1; the maximum

value is limited to the QXY divide ratio − 1; QXY refers to the

distribution dividers on each output, where x is either 0

(for PLL0) or 1 (for PLL1), and y is A, B, or C

Embedded Frequency

fOUT ÷ (228 − 1)

fOUT ÷ 6

fOUT is the output frequency

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