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AD9543 Datasheet(PDF) 8 Page - Analog Devices

Part # AD9543
Description  Quad Input, 10-Output, Dual DPLL/IEEE 1588 Synchronizer and Jitter Cleaner
PDF  66 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9543 Datasheet(HTML) 8 Page - Analog Devices

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AD9543
Data Sheet
Rev. 0 | Page 8 of 66
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE DEMODULATOR
Carrier Frequency
(Sync Edge = 1, 2, 3)
Band 0
DC Balanced Modulation
0.5
30
MHz
Unbalanced modulation
0.5
45
MHz
Band 1
DC Balanced Modulation
1
90
MHz
Unbalanced modulation
1
135
MHz
Embedded Clock Rate
1
fOUT/6
Hz
fOUT is the nominal output frequency of the output
with the embedded clock
Duty Cycle Deviation
tSYS = 1/(fSYS); the system clock frequency is fOSC/J × K × D,
where fOSC is the frequency of the system clock
oscillator connected to the XOA/XOB pins, J is the
SYSCLK input divider ratio, K is the feedback divider
ratio, and D is the SYSCLK doubler setting; D = 2 if the
SYSCLK doubler is enabled, and D = 1 if it is disabled;
tSYS must be in the 414 ps to 440 ps range; fOUT is the
output frequency
DC Balanced Modulation
tSYS × 5/3
1/(4 × fOUT)
sec
Unbalanced Modulation
tSYS × 5/2
1/(4 × fOUT)
sec
Polarity Detection Enabled
tSYS × 5
1/(4 × fOUT)
sec
REFERENCE MONITORS
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE MONITORS
Reference Monitor
Loss of Reference Detection Time
4.9 + 0.13 × tPFD
μs
tPFD is the nominal phase detector period,
R/fREF, where R is the frequency division factor
determined by the R divider, and fREF is the
frequency of the active reference
Frequency Out of Range Limits
50
1.5 × 107
ppb
Parts per billion (ppb) is defined as
(Δf/fREF) × 109, where Δf is the frequency
deviation, and fREF is the reference input
frequency; programmable with the lower
bound, subject to quality of the system clock
(or the source of system clock compensation);
1.5 × 107 is equivalent to 1.5%
Validation Timer
0.001
1048
sec
Programmable in 1 ms increments
Excess Jitter Alarm Threshold
1
65535
ns
Programmable in 1 ns increments



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