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AD9543 Datasheet(PDF) 11 Page - Analog Devices

Part # AD9543
Description  Quad Input, 10-Output, Dual DPLL/IEEE 1588 Synchronizer and Jitter Cleaner
PDF  66 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9543 Datasheet(HTML) 11 Page - Analog Devices

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Data Sheet
AD9543
Rev. 0 | Page 11 of 66
DIGITAL PLL (DPLL0, DPLL1) SPECIFICATIONS
Table 10.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL PLL
Digital Phase Detector (DPD)
Input Frequency Range
1
2 × 105
Hz
Loop Filter
Profile 0
Bandwidth
0.0001
1850
Hz
Programmable design parameter; (fPFD/bandwidth) ≥ 20
Phase Margin
70
Degrees
Closed-Loop Peaking
1.1
dB
Profile 1
Bandwidth
0.0001
305
Hz
Programmable design parameter; (fPFD/bandwidth) ≥ 20
Phase Margin
88.5
Degrees
Closed-Loop Peaking
0.1
dB
In accordance with Telcordia GR-253-CORE jitter transfer
specifications
DIGITAL PLL NCO Division Ratio
These specifications cover limitations on the DPLLx frequency
tuning word (FTW0); the AD9543 evaluation software frequency
planning wizard sets these values automatically for the user, and
the AD9543 evaluation software is available for download from
the AD9543 product page; NCO division = 248/FTW0, which takes
the form INT.FRAC, where INT is the integer portion, and FRAC is
the fractional portion
NCO Integer
7
13
This is the integer portion of NCO division ratio
NCO Fraction
0.05
0.95
This is the fractional portion of NCO division ratio
DIGITAL PLL LOCK DETECTION SPECIFICATIONS
Table 11.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE LOCK DETECTOR
Threshold Programming Range
10
224 − 1
ps
Threshold Resolution
1
ps
FREQUENCY LOCK DETECTOR
Threshold Programming Range
10
224 − 1
ps
Threshold Resolution
1
ps
PHASE STEP DETECTOR
Threshold Programming Range
100
232 − 1
ps
Setting this value too low causes false triggers
Threshold Resolution
1
ps



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