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AD9543 Datasheet(PDF) 37 Page - Analog Devices

Part # AD9543
Description  Quad Input, 10-Output, Dual DPLL/IEEE 1588 Synchronizer and Jitter Cleaner
PDF  66 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9543 Datasheet(HTML) 37 Page - Analog Devices

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Data Sheet
AD9543
Rev. 0 | Page 37 of 66
SMALL CELL BASE STATION
In this application (shown in Figure 42), the AD9543 provides
all of the synchronization to the baseband unit of a small cell
base station. The built in JESD204B support enables a
particularly compact and efficient design.
The AD9543 can lock to any of the following: GPS, SyncE,
and/or IEEE 1588 (requires a separate IEEE 1588 servo and
software stack) or loop timed (if using SONET/SDH backhaul).
See Figure 43 for details about implementing IEEE 1588 Version 2
or Version 3 with the AD9543. The AD9543, when used in
conjunction with an IEEE 1588 servo and software stack, can
also operate using a hybrid combination of these inputs (that is,
SyncE, GPS) as defined in assisted partial timing operation.
The PLL0 of the AD9543 provides one device clock and up to
four device system reference clocks that can be used to clock
wireless transceivers, such as the AD9371.
The PLL1 of the AD9543 clocks the backhaul interface and,
optionally, the CPU interface.
The EEPROM support of the AD9543 allows the AD9543 to
load its configuration automatically at power-up.
INPUT
GPS, LOOP TIMED
FROM NETWORK
SyncE
RADIO
(2 CARDS)
EXTERNAL
NETWORK
ETHERNET
SyncE
PASSIVE OPTICAL NETWORK
SONET/SDH
IEEE 1588
SYSREF TO
RADIO 1
SYSREF TO
RADIO 2
SYSREF TO
BASEBAND
1:4
FANOUT
BASEBAND
PROCESSOR
NETWORK
CONNECTION
30.72MHz
61.44MHz
122.88MHz
245.76MHz
307.2MHz
10MHz
25MHz
125MHz
156.25MHz
312.5MHz
30.72MHz
61.44MHz
122.88MHz
JESD204B SUPPORT
SYSTEM
CLOCK PLL
STATUS AND
CONTROL
PINS
AD9543
TEMPERATURE
SENSOR
SYSTEM CLOCK
COMPENSATION
REFERENCE
MONITORS
TDC
REFERENCE INPUTS
NCO
DPLL
DPLL0
PLL
APLL0
VCO
NCO
DPLL
DPLL1
PLL
APLL1
VCO
PLL0
PLL1
DISTRIBUTION
OUTPUTS
DISTRIBUTION
OUTPUTS
÷2
÷Q
÷R
OUT0AP,
OUT0AN,
OUT0BP,
OUT0BN,
OUT0CP,
OUT0CN
OUT1AP,
OUT1AN,
OUT1BP,
OUT1BN
XOA,
XOB
INTERNAL ZERO DELAY
INTERNAL ZERO DELAY
EEPROM
(OPTIONAL)
SYSTEM
CLOCK
DIGITAL
CROSS
POINT
MUX
SERIAL PORT (SPI/I2C)
AND EEPROM
CONTROLLER
M0 TO M6
REFERENCE
SWITCHING
CONTROL
REFA,
REFAA,
REFB,
REFBB
÷2
÷Q
AUXILIARY
NCOs
AUXILIARY
TDCs
Figure 42. AD9543 Small Cell Application



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