AD9548 datasheet(33/111 Pages) AD

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Data Sheet

AD9548

Rev. G | Page 33 of 111

The DPLL includes a feedback divider that causes the DDS to

operate at an integer-plus-fractional multiple (S + 1 + U/V) of

fTDC. S is the 30-bit value stored in the profile register and has a

range of 7 ≤ S ≤ 1,073,741,823. U and V are the 10-bit numerator

and denominator values of the optional fractional divide

component and are also stored in the profile register. Together

they establish the nominal DDS frequency (fDDS), given by

















DDS

Normally, fractional-N designs exhibit distinctive phase noise

and spurious artifacts resulting from the modulation of the

integer divider based on the fractional value. Such is not the

case for the AD9548 because it uses a purely digital means to

determine phase errors. Because the phase errors incurred by

modulating the feedback divider are deterministic, it is possible

to compensate for them digitally. The result is a fractional-N

PLL with no discernable modulation artifacts.

TDC/PFD

The TDC is a highly integrated functional block that

incorporates both analog and digital circuitry. There are two

pins associated with the TDC that the user must connect to

external components. Figure 40 shows the recommended

component values and their connections.

For best performance, place components as close as possible to

the device pins. Components with low effective series resistance

(ESR) and low parasitic inductance yield the best results.

AD9548

10µF

0.1µF

TDC_VRT

TDC_VRB

Figure 40. TDC Pin Connections

The phase-frequency detector (PFD) is an all-digital block. It

compares the digital output from the TDC (which relates to the

active reference edge) with the digital word from the feedback

block (which relates to the rollover edge of the DDS

accumulator after division by the feedback divider). It uses a

digital code pump and digital integrator (rather than a

conventional charge pump and capacitor) to generate the error

signal that steers the DDS frequency toward phase lock.

Closed-Loop Phase Offset

The all-digital nature of the TDC/PFD provides for numerical

control of the phase offset between the reference and feedback

edges. This allows the user to adjust the relative timing of the

distribution output edges relative to the reference input edges

by programming the 40-bit fixed phase lock offset register

(Address 0x030F to Address 0x0313). The 40-bit word is a

signed (twos complement) number that represents units of

picoseconds.

In addition, the user can adjust the closed-loop phase offset

(positive or negative) in incremental fashion. To do so, program

the desired step size in the 16-bit incremental phase lock offset

step size register (Address 0x0314 to Address 0x0315). This is

an unsigned number that represents units of picoseconds. The

programmed step size is added to the current closed-loop phase

offset each time the user writes a Logic 1 to the increment phase

offset bit (Register 0x0A0C, Bit 0). Conversely, the programmed

step size is subtracted from the current closed-loop phase offset

each time the user writes a Logic 1 to the decrement phase offset

bit (Register 0x0A0C, Bit 1). The serial input/output port

control logic clears both of these bits automatically. The user can

remove the incrementally accumulated phase by writing a Logic 1

to the reset incremental phase offset bit (Register 0x0A0C, Bit 2),

which is also cleared automatically. Alternatively, rather than

using the serial input/output port, the multifunction pins can be

set up to perform the increment, decrement, and clear functions.

Note that the incremental phase offset is completely independent of

the offset programmed into the fixed phase lock offset register.

However, if the phase slew limiter is active (see the Hitless

Reference Switching (Phase Slew Control) section), then any

instantaneous change in closed-loop phase offset (fixed or

incremental) will be subject to possible slew limitation by the

action of the phase slew limiter.

Programmable Digital Loop Filter

The AD9548 loop filter is a third order digital IIR filter that is

analogous to the third order analog loop shown in Figure 41.

Figure 41. Third Order Analog Loop Filter

The filter requires four coefficients as shown in Figure 42.

The AD9548 evaluation board software automatically generates

the required loop filter coefficient values based on the user’s

design criteria. The Calculating Digital Filter Coefficients

section contains the design equations for calculating the loop

filter coefficients manually.

LOOP FILTER

(THIRD ORDER IIR)

OUT

FRACTIONAL

(16-BIT)

1/2x

(6-BIT)

(3-BIT)

(4-BIT)

FRACTIONAL

(17-BIT)

1/2x

(6-BIT)

FRACTIONAL

(17-BIT)

1/2x

(6-BIT)

FRACTIONAL

(15-BIT)

1/2x

(5-BIT)

Figure 42. Third Order Digital IIR Loop Filter

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