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AD9548 Datasheet(PDF) 55 Page - Analog Devices |
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AD9548 Datasheet(HTML) 55 Page - Analog Devices |
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55 / 111 page  Data Sheet AD9548 Table 33. Serial Control Port Timing Parameter Description tDS Setup time between data and the rising edge of SCLK. tDH Hold time between data and the rising edge of SCLK. tCLK Period of the clock. tS Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle). tC Setup time between the SCLK rising edge and the CS rising edge (end of the communication cycle). To ensure that SDIO/SDO do not tristate before the last data bit (D0) is read, it is recommended that a ½ SCLK cycle be used for tC. tHI Minimum period that SCLK should be in a logic high state. tLO Minimum period that SCLK should be in a logic low state. tDV SCLK to valid SDIO and SDO (see Figure 59). Rev. G | Page 55 of 111 |
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