AD9548 datasheet(41/111 Pages) AD

41 / 111 page

Data Sheet

AD9548

logic to control enable/disable activity to avoid the production

of runt pulses and ensure that outputs with the same divide

ratios become active/inactive in unison.

Output Mode

The user has independent control of the operating mode of

each of the four output channels via the distribution channel

modes register (Address 0x0404 to Address 0x0407). The

operating mode control includes

•

Logic family and pin functionality

•

Output drive strength

•

Output polarity

The three least significant bits of each of the four distribution

channel mode registers comprise the mode bits. The mode

value selects the desired logic family and pin functionality of an

output channel, as given in Table 24.

Table 24. Output Channel Logic Family and Pin Functionality

Mode Bits [2:0]

Logic Family and Pin Functionality

000

CMOS (both pins)

001

CMOS (positive pin); tristate (negative pin)

010

Tristate (positive pin); CMOS (negative pin)

011

Tristate (both pins)

100

LVDS

101

LVPECL

110

Unused

111

Unused

Regardless of the selected logic family, each is capable of dc

operation. However, the upper frequency is limited by the load

conditions, drive strength, and impedance matching inherent in

each logic family. Practical limitations set the maximum CMOS

frequency to approximately 250 MHz, whereas LVPECL and

LVDS are capable of 725 MHz.

In addition to the three mode bits, each of the four distribution

channel mode registers includes the following control bits:

•

Polarity invert

•

CMOS phase invert

•

Drive strength

The polarity invert bit enables the user to choose between

normal polarity and inverted polarity. Normal polarity is the

default state. Inverted polarity reverses the representation of

Logic 0 and Logic 1 regardless of the logic family.

The CMOS phase invert bit applies only when the mode bits

select the CMOS logic family. In CMOS mode, both output pins

of the channel have a dedicated CMOS driver. By default, both

drivers deliver identical signals. However, setting the CMOS

phase invert bit causes the signal on an OUTxN pin to be the

opposite of the signal appearing on the OUTxP pin.

The drive strength bit allows the user to control whether the output

uses weak (0) or strong (1) drive capability (applies to CMOS

and LVDS but not LVPECL). For the CMOS family, the strong

setting implies normal CMOS drive capability, whereas the

weak setting implies low capacitive loading and allows for reduced

EMI. For the LVDS family, the weak setting provides 3.5 mA

drive current for standard LVDS operation, whereas the strong

setting provides 7 mA for double terminated or double voltage

LVDS operation. Note that 3.5 mA and 7 mA are the nominal

drive current values when using the internal current setting resistor.

Output Current Control with an External Resistor

By default, the output drivers have an internal current setting

resistor (3.12 kΩ nominal) that establishes the nominal drive

current for the LVDS and LVPECL operating modes. Instead of

using the internal resistor, the user can set the external distribution

resistor bit (Register 0x0400, Bit 5) and connect an external resistor

to the OUT_RSET pin. Note that this feature supports an

external resistor value of 3.12 kΩ only, allowing for tighter

control of the output current than is possible by using the

internal current setting resistor. However, if the user elects to

use a nonstandard external resistance, the following equations

provide the output drive current as a function of the external

resistance (R):

LVDS

8325

0 =

LVDS

665

1 =

ILVPECL

The numeric subscript associated with the LVDS output current

corresponds to the logic state of the drive strength bit in the

distribution channel modes register (Address 0x0404 to

Address 0x00407). For R = 3.12 kΩ, the equations yield ILVDS0 =

3.5 mA, ILVDS1 = 7.0 mA, and ILVPECL = 8.0 mA. Note that the device

maintains a constant 1.238 V (nominal) across the external resistor.

Clock Distribution Synchronization

A block diagram of the distribution synchronization

functionality appears in Figure 50. The synchronization

sequence begins with the primary synchronization signal,

which ultimately results in delivery of a synchronization strobe

to the clock distribution logic.

As indicated, the primary synchronization signal originates

from four possible sources.

•

Direct sync source via the sync distribution bit

(Register 0x0A02, Bit 1)

•

Automatic sync source based on frequency or phase lock

detection as controlled via the automatic synchronization

•

Multifunction pin sync source via one of the multifunction

pins (M0 to M7)

•

EEPROM sync source via the EEPROM

All four sources of the primary synchronization signal are logic

OR’ed, so any one of them can synchronize the clock

distribution output at any time. When using the multifunction

pins, the synchronization event is the falling edge of the selected

Rev. G | Page 41 of 111

AD9548 Datasheet(PDF) 41 Page - Analog Devices

AD9548 Datasheet(HTML) 41 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL