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Data Sheet

AD9548

Rev. G | Page 25 of 111

Program the Digital Phase-Locked Loop (DPLL)

The DPLL parameters reside in the 0x0300 register address

space. They include the following:



Free-run frequency (DDS frequency tuning word)



DDS phase offset



DPLL pull-in range limits



DPLL closed-loop phase offset



Phase slew control (for hitless reference switching)



Tuning word history control (for holdover operation)

Program the Clock Distribution Outputs

The clock distribution parameters reside in the 0x0400 register

address space. They include the following:



Output power-down control



Output enable (disabled by default)



Output synchronization



Output mode control



Output divider functionality

Program the Reference Inputs

The reference input parameters reside in the 0x0500 register

address space. They include the following:



Reference power-down



Reference logic family



Reference profile assignment control



Phase build-out control

Program the Reference Profiles

The reference profile parameters reside in the 0x0600 to 0x0700



Reference priority



Reference period



Reference period tolerance



Reference validation timer



Reference redetect timer



Digital loop-filter coefficients



Reference prescaler (R-divider)



Feedback dividers (S, U, and V)



Phase and frequency lock detector controls

Generate the Reference Acquisition

After the registers are programmed, issue an input/output

update using Register 0x0005, Bit 0 to invoke all of the register

settings programmed up to this point.

If the settings are programmed for manual profile assignment,

the DPLL locks to the first available reference that has the

highest priority. If the settings are programmed for automatic

profile assignment, then write to the reference profile detect

require starting. Next, issue an input/output update

(Address 0x0005, Bit 0) to start the selected state machines.

Upon completion of the reference detection sequence, the

DPLL locks to the first available reference with the highest

priority.

Generate the Output Clock

If the registers are programmed for automatic clock distribution

synchronization via DPLL phase or frequency lock, the synthesized

output signal appears at the clock distribution outputs

(assuming the output is enabled and that the DDS output signal

has been routed to the CLKIN input pins). Otherwise, set and

then clear the sync distribution bit (Address 0x0A02, Bit 1) or

use a multifunction pin input (if programmed accordingly) to

generate a clock distribution sync pulse, which causes the

synthesized output signal to appear at the clock distribution

outputs.

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