AD9548 datasheet(52/111 Pages) AD

52 / 111 page

AD9548

Data Sheet

SPI Mode Operation

The SPI port supports both 3-wire (bidirectional) and 4-wire

(unidirectional) hardware configurations and both MSB-first

and LSB-first data formats. Both the hardware configuration

and data format features are programmable. By default, the

AD9548 uses the bidirectional MSB-first mode. The reason that

bidirectional is the default mode is so that the user can still

write to the device, if it is wired for unidirectional operation, to

switch to unidirectional mode.

Assertion (active low) of the CS pin initiates a write or read

operation to the AD9548 SPI port. For data transfers of three

bytes or fewer (excluding the instruction word), the device

supports the CS stalled high mode (see Table 30). In this mode,

the CS pin can be temporarily deasserted on any byte boundary,

allowing time for the system controller to process the next

byte. CS can be deasserted only on byte boundaries, however.

This applies to both the instruction and data portions of the

transfer.

During stall high periods, the serial control port state machine

enters a wait state until all data is sent. If the system controller

decides to abort a transfer midstream, then the state machine must

be reset by either completing the transfer or by asserting the CS pin

for at least one complete SCLK cycle (but less than eight SCLK

cycles). Deasserting the CS pin on a nonbyte boundary

terminates the serial transfer and flushes the buffer.

In the streaming mode (see Table 30), any number of data bytes

can be transferred in a continuous stream. The register address

is automatically incremented or decremented. CS must be

deasserted at the end of the last byte transferred, thereby ending

the stream mode.

Table 30. Byte Transfer Count

Bytes to Transfer

Streaming mode

Communication Cycle—Instruction Plus Data

The SPI protocol consists of a two-part communication cycle.

The first part is a 16-bit instruction word that is coincident with

the first 16 SCLK rising edges and a payload. The instruction

word provides the AD9548 serial control port with information

regarding the payload. The instruction word includes the R/W

bit that indicates the direction of the payload transfer (that is, a

read or write operation). The instruction word also indicates

the number of bytes in the payload and the starting register

address of the first payload byte.

Write

If the instruction word indicates a write operation, the payload

is written into the serial control port buffer of the AD9548.

Data bits are registered on the rising edge of SCLK. The length of

the transfer (1, 2, or 3 bytes or streaming mode) depends on the

W0 and W1 bits (see Table 30) in the instruction byte. When

not streaming, CS can be deasserted after each sequence of

eight bits to stall the bus (except after the last byte, where it ends

the cycle). When the bus is stalled, the serial transfer resumes

when CS is asserted. Deasserting the CS pin on a nonbyte

boundary resets the serial control port. Reserved or blank

registers are not skipped over automatically during a write

sequence. Therefore, the user must know what bit pattern to

write to the reserved registers to preserve proper operation of

the part. Generally, it does not matter what data is written to blank

registers, but it is customary to write 0s.

Most of the serial port registers are buffered (see the

Buffered/Active Registers section for details on the difference

between buffered and active registers). Therefore, data written

into buffered registers does not take effect immediately. An

additional operation is needed to transfer buffered serial control

port contents to the registers that actually control the device.

This is accomplished with an input/output update operation,

which is performed in one of two ways. One is by writing a

Logic 1 to Register 0x0005, Bit 0 (this bit is self-clearing). The

other is to use an external signal via an appropriately

programmed multifunction pin. The user can change as many

The input/output update operation transfers the buffer register

contents to their active register counterparts.

Read

The AD9548 supports the long instruction mode only. If the

instruction word indicates a read operation, the next N × 8

SCLK cycles clock out the data from the address specified in the

instruction word. N is the number of data bytes read and

depends on the W0 and W1 bits of the instruction word.

During a SPI read, serial data on SDIO (or SDO in the case of

4-wire mode) transitions on the SCLK falling edge and is

normally sampled on the SCLK rising edge. To read the last bit

correctly, the SPI host must be able to tolerate a zero hold time. If

zero hold time is not possible, the user can either use streaming

mode and delay the rising edge of CS, or sample the serial data on

the SCLK falling edge. However, to sample the data on the

SCLK falling edge correctly, the user must ensure that the setup

time is greater than tDV (time data valid). Blank registers are not

skipped over during readback.

A readback operation takes data from either the serial control

port buffer registers or the active registers, as determined by

Rev. G | Page 52 of 111

AD9548 Datasheet(PDF) 52 Page - Analog Devices

AD9548 Datasheet(HTML) 52 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL