AD9548 datasheet(23/111 Pages) AD

23 / 111 page

Data Sheet

AD9548

Rev. G | Page 23 of 111

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

AD9548

HIGH

IMPEDANCE

INPUT

DOWNSTREAM

DEVICE

0.1µF

3.3V LVDS

OUTPUT

Figure 28. AC-Coupled LVDS or LVPECL Output Driver

AD9548

DOWNSTREAM

DEVICE

3.3V

LVPECL-

COMPATIBLE

OUTPUT

Figure 29. DC-Coupled LVDS or LVPECL Output Driver

0.1µF

AD9548

SELF-BIASED

REFERENCE

INPUT

Figure 30. Reference Input

0.1µF

AD9548

SELF-BIASED

SYSCLK

INPUT

Figure 31. SYSCLKx Input

0.1µF

AD9548

SELF-BIASED

CLKINx

INPUT

Figure 32. CLKINx Input

SYSCLKP

300Ω

150Ω

0.1µF

SYSCLKN

AD9548

3.3V

CMOS

TCXO

0.1µF

Figure 33. System Clock Input (SYSCLKP/SYSCLKN) When Using a

TCXO/OCXO with 3.3 V CMOS Output

SYSCLKP

SYSCLKN

AD9548

10MHz TO 50MHz FUNDAMENTAL

AT-CUT CRYSTAL WITH 10pF

LOAD CAPACITANCE (CLOAD)

15pF

0Ω

(OPTIONAL)

NOTES

1. THE RECOMMENDED CLOAD = 10pF IS SHOWN. THE VALUES OF THE 15pF

SHUNT CAPACITORS SHOWN HERE MUST EQUAL 2 × (CLOAD − CSTRAY),

WHERE CSTRAY IS TYPICALLY 2pF TO 5pF). THE SERIES RESISTOR

CONNECTED TO SYSCLKN IS NORMALLY NOT REQUIRED, BUT CAN BE

USEFUL TO LIMIT THE POWER DISSIPATED IN THE CRYSTAL.

Figure 34. System Clock Input (XOA/XOB) in Crystal Mode

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