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SI5321 Datasheet(PDF) 22 Page - List of Unclassifed Manufacturers |
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SI5321 Datasheet(HTML) 22 Page - List of Unclassifed Manufacturers |
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22 / 34 page  Si5321 22 Rev. 2.3 2.13. Design and Layout Guidelines Precision clock circuits are susceptible to board noise and EMI. To take precautions against unacceptable levels of board noise and EMI affecting performance of the Si5321, consider the following: Power the device from 3.3 V since the internal regulator provides >40 dB of isolation to the VDD25 pins (which power the PLL circuitry). When powering the device from 3.3 V, use an isolated, local plane to connect the VDD25 pins. Avoid running signal traces over or below this plane without a ground plane in between. Route all I/O traces between ground planes as much as possible Maintain an input clock amplitude in the 200 mVPP to 500 mVPP differential range. Excessive high-frequency harmonics of the input clock should be minimized. The use of filters on the input clock signal can be used to remove high- frequency harmonics. |
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