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SI5321 Datasheet(PDF) 28 Page - List of Unclassifed Manufacturers |
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SI5321 Datasheet(HTML) 28 Page - List of Unclassifed Manufacturers |
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28 / 34 page ![]() Si5321 28 Rev. 2.3 H4 VALTIME I* LVTTL* Clock Validation Time for LOS. VALTIME sets the clock validation times for recovery from an LOS alarm condition. When VALTIME is high, the validation time is approximately 100 ms. When VALTIME is low, the validation time is approx- imately 2 ms. H3 RSTN/CAL I* LVTTL* Reset/Calibrate. When low, all LVTTL outputs are forced into a high impedance state, the DSPLL is forced out-of-lock, and the device control logic is reset. A low-to-high transition on RSTN/CAL initializes all digital logic to a known condition and initiates self- calibration of the DSPLL. At the completion of self- calibration, the DSPLL begins to lock to the selected clock input signal and begins to drive out the output clock signal onto the CLKOUT pins. F8 LOS O LVTTL Loss-of-Signal (LOS) Alarm for CLKIN. Active high output indicates that the Si5321 has detected missing pulses on the input clock signal. The LOS alarm is cleared after either 100 ms or 13 s of a valid CLKIN clock input, depending on the set- ting of the VALTIME input. D8 DH_ACTV O LVTTL Digital Hold Mode Active. Active high output indicates that the DSPLL is in digital hold mode. Digital hold mode locks the current state of the DSPLL and forces the DSPLL to continue generation of the output clock with no additional phase or frequency information from the input clock. E8 CAL_ACTV O LVTTL Calibration Mode Active. This output is driven high during the DSPLL self-cal- ibration and the subsequent initial lock acquisition period. C2 VSEL33 I* LVTTL* Select 3.3 V VDD Supply. This is an enable pin for the internal regulator. To enable the regulator, connect this pin to the VDD33 pins. D3–D5, E3–E5 VDD33 VDD Supply 3.3 V Supply. 3.3 V power is applied to the VDD33 pins. Typical supply bypassing/decoupling for this configuration is indicated in the typical application diagram for 3.3 V supply operation. Table 10. Si5321 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description *Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a logic low state if the input is not driven from an external source. |
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