Si5321

14

Rev. 2.3

Clock Output Wander with

Stable Input Clock;

Temperature

Gradient <10

°C/min;

800 Hz Loop BW

—

—

45

ps/

°C/

min

Initial Frequency Accuracy in Digital Hold

Mode (first 100 ms with voltage and

temperature held constant)

Stable Input Clock

Selected until entering

Digital Hold

—

—

5.5

ppm

Clock Output Frequency Accuracy Over

Temperature in Digital Hold Mode

Constant Supply Voltage

—

17.2

30

ppm

/

°C

Clock Output Frequency Accuracy Over

Supply Voltage in Digital Hold Mode

Constant Temperature

—

—

600 ppm

/V

When hitlessly recovering

from Digital Hold mode

–200

0

200

ps

(See Figure 8)

BWSEL[1:0] = 11, BWBOOST = 0

BWSEL[1:0] = 00, BWBOOST = 0

BWSEL[1:0] = 01, BWBOOST = 0

BWSEL[1:0] = 10, BWBOOST = 0

When hitlessly recovering

from Digital Hold mode

6400 Hz, No Scaling

3200 Hz, No Scaling

1600 Hz, No Scaling

800 Hz, No Scaling

—

—

—

—

—

—

—

—

10

5

2.5

1.25

ps/

µs

Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)

Parameter

Symbol

Test Condition

Min

Typ

Max Unit

Notes:

1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.

2. For reliable device operation, temperature gradients should be limited to 10 °C/min.

3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms

of nanoseconds per millisecond. The equivalent ps/

µs unit is used here since the maximum phase transient magnitude

for the Si5321 (tPT_MTIE) never reaches one nanosecond.