Si5321

Rev. 2.3

29

D6, D7, E6,

E7, F3–F7

Supply

2.5 V Supply.

These pins provide a means of connecting the

compensation network for the on-chip regulator.

C3–C7, E2,

F2, G2–G8

GND

GND

Supply

Ground.

Must be connected to system ground. Minimize the

ground path impedance for optimal performance of

the device.

H2

REXT

I

Analog

External Biasing Resistor.

Used by on-chip circuitry to establish bias currents

within the device. This pin must be connected to

GND through a 10 k

Ω (1%) resistor.

A4–8, B5, B8

RSVD_NC

LVTTL

Reserved—No Connect.

This pin must be left unconnected for normal

operation.

B6, B7, C8

RSVD_GND

LVTTL

Reserved—GND.

This pin must be tied to GND for normal operation.

Table 10. Si5321 Pin Descriptions (Continued)

Pin #

Pin Name

I/O

Signal Level

Description

*Note:

The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a

logic low state if the input is not driven from an external source.