56F8014 datasheet(3/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 3

Freescale Semiconductor

Preliminary

56F8014 Block Diagram

Program Controller

and Hardware

Looping Unit

Data ALU

16 x 16 + 36 -> 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

Address

Generation Unit

Bit

Manipulation

Unit

16-Bit

56800E Core

Interrupt

Controller

Unified Data /

Program RAM

4KB

PDB

XAB1

XAB2

XDB2

CDBR

SPI or I2C

or Timer

or GPIOB

IPBus Bridge (IPBB)

System Bus

Control

R/W Control

Memory

PAB

CDBW

CDBR

CDBW

JTAG/EOnCE

Port or

GPIOD

Digital Reg

Analog Reg

Low-Voltage

Supervisor

VCAP

VDD

VSS_IO VDDA

VSSA

RESET

Timer or

GPIOB

AD0

Clock

Generator*

System

Integration

Module

PWM Outputs

PWM

or Timer Port

or GPIOA

*Includes On-Chip

Relaxation Oscillator

COP/

Watchdog

AD1

Program Memory

8K x 16 Flash

ADC

GPIOC

SCI

or I2C

or GPIOB

• Up to 32 MIPS at 32MHz core frequency

• DSP and MCU functionality in a unified,

C-efficient architecture

• 16KB Program Flash

• 4KB Unified Data/Program RAM

• One 5-channel PWM module

• Two 4-channel 12-bit ADCs

• One Serial Communication Interface (SCI) with LIN

slave functionality

• One Serial Peripheral Interface (SPI)

• One 16-bit Quad Timer

• One Inter-Integrated Circuit (I

2C) Port

• Computer Operating Properly (COP)/Watchdog

• On-Chip Relaxation Oscillator

• Integrated Power-On Reset and Low-Voltage Interrupt

Module

• JTAG/Enhanced On-Chip Emulation (OnCE™) for

unobtrusive, real-time debugging

• Up to 26 GPIO lines

• 32-pin LQFP Package

56F8014 General Description

56F8014 Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc

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