56F8014 datasheet(57/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 3

Freescale Semiconductor

Preliminary

5.6.10

Fast Interrupt 1 Match Register (FIM1)

Figure 5-12 Fast Interrupt 1 Match Register (FIM1)

5.6.10.1

Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.10.2

Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0

These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service

routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table

first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast

Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority

level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt.

Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to

the vector table.

5.6.11

Fast Interrupt 1 Vector Address Low Register (FIVAL1)

Figure 5-13 Fast Interrupt 1 Vector Address Low Register (FIVAL1)

5.6.11.1

Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0

The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1

to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.

5.6.12

Fast Interrupt 1 Vector Address High Register (FIVAH1)

Figure 5-14 Fast Interrupt 1 Vector Address High Register (FIVAH1)

5.6.12.1

Reserved—Bits 15–5

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

Base + $9

Read

FAST INTERRUPT 1

Write

RESET

00000000

Base + $A

Read

FAST INTERRUPT 1 VECTOR ADDRESS LOW

Write

RESET

00000000

Base + $B

Read

FAST INTERRUPT 1 VECTOR

ADDRESS HIGH

Write

RESET

00000000

56F8014 Datasheet(PDF) 57 Page - Freescale Semiconductor, Inc

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