56F8014 datasheet(9/124 Pages) FREESCALE

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Architecture Block Diagram

56F8014 Technical Data, Rev. 3

Freescale Semiconductor

Preliminary

Figure 1-2 Peripheral Subsystem

Table 1-1 Bus Signal Names

Name

Function

Program Memory Interface

pab[20:0]

Program memory address bus. Data is returned on pdb_m bus.

pdb_m[15:0]

Program data bus for instruction word fetches or read operations.

cdbw[15:0]

Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus

are used for writes to program memory.)

Primary Data Memory Interface Bus

xab1[23:0]

Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written

on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.

1. Byte accesses can only occur in the bottom half of the memory address space. The Most Significant Bit (MSB) of the

address will be forced to 0.

cdbr_m[31:0]

Primary core data bus for memory reads. Addressed via xab1 bus.

cdbw[31:0]

Primary core data bus for memory writes. Addressed via xab1 bus.

Secondary Data Memory Interface

xab2[23:0]

Secondary data address bus used for the second of two simultaneous accesses. Capable of

addressing only words. Data is returned on xdb2_m.

xdb2_m[15:0]

Secondary data bus used for secondary data address bus xab2 in the dual memory reads.

IPBus

GPIO A

Interrupt

Controller

To/From IPBus Bridge

GPIO B

GPIO C

CLKGEN

(ROSC / PLL /

CLKIN)

POR & LVI

SIM

GPIO D

Low-Voltage Interrupt

System POR

COP Reset

RESET / GPIOA7

COP

GPIOAn

GPIOBn

GPIOCn

GPIODn

(Continues on Figure 1-3)

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