56F8014 datasheet(18/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 3

Freescale Semiconductor

Preliminary

GPIOB5

(T1)

(FAULT3)

Input/

Output

Input/

Output

Input, pulled

high

internally

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

T1 — Timer, Channel 1

FAULT3 — This fault input pin is used for disabling selected PWM

outputs in cases where fault conditions originate off-chip.

After reset, the default state is GPIOB5. The peripheral functionality

is controlled via the SIM. See Section 6.3.8.

TCK

(GPIOD2)

Input

Input/

Output

Input, pulled

high

internally

Test Clock Input — This input pin provides a gated clock to

synchronize the test logic and shift serial data to the JTAG/EOnCE

port. The pin is connected internally to a pull-up resistor. A Schmitt

trigger input is used for noise immunity.

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is TCK.

TMS

(GPIOD3)

Input

Input/

Output

Input, pulled

high

internally

Test Mode Select Input — This input pin is used to sequence the

JTAG TAP controller’s state machine. It is sampled on the rising

edge of TCK and has an on-chip pull-up resistor.

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is TMS.

TDI

(GPIOD0)

Input

Input/

Output

Input, pulled

high

internally

Test Data Input — This input pin provides a serial input data stream

to the JTAG/EOnCE port. It is sampled on the rising edge of TCK

and has an on-chip pull-up resistor.

Port D GPIO — This GPIO pin can be individually programmed as

an input or output pin.

After reset, the default state is TDI.

Return to Table 2-2

Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

Type

State During

Reset

Signal Description

56F8014 Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc

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