56F8014 datasheet(71/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 3

Freescale Semiconductor

Preliminary

Figure 6-10 GPIO Peripheral Select Register (SIM_GPS)

6.3.8.1

TMR Clock Rate (TCR)—Bit 15

This bit selects the clock speed for the TMR module.

•

0 = TMR module clock rate equals core clock rate, typically 32MHz (default)

•

1 = TMR module clock rate equals three times core clock rate

Note: This bit should only be changed while the TMR module’s clock is disabled. See Section 6.3.9.

Note: High-speed clocking is only available when the PLL is being used.

Note: If the PWM reload pulse is used as input to Timer 3 (See SIM_CTRL: TC3_INP, Section 6.3.1.7),

then the clocks of the Quad Timer and PWM must be related, as shown in Table 6-2.

6.3.8.2

PWM Clock Rate (PCR)—Bit 14

This bit selects the clock speed for the PWM module.

•

0 = PWM module clock rate equals core clock rate, typically 32MHz (default)

•

1 = PWM module clock rate equals three times core clock rate

Note: This bit should only be changed while the PWM module’s clock is disabled. See Section 6.3.9.

Note: High-speed clocking is only available when the PLL is being used.

Note: If the PWM reload pulse is used as input to Timer 3 (See SIM_CTRL: TC3_INP, Section 6.3.1.7),

then the clocks of the Quad Timer and PWM must be related, as shown in Table 6-2.

Base + $B

Read

TCR

PCR

CFG_

CFG_A5

CFG_A4

Write

RESET

0000

00000000

0000

Table 6-2 Allowable Quad Timer and PWM Clock Rates

when Using PWM Reload Pulse

Quad Timer

Clock Speed

PWM

56F8014 Datasheet(PDF) 71 Page - Freescale Semiconductor, Inc

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