56F8014 datasheet(73/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 3

Freescale Semiconductor

Preliminary

6.3.8.10

Configure GPIOB1 (CFG_B1)—Bit 5

This bit selects the alternate function for GPIOB1.

•0 = SS (default)

•1 = SDA

6.3.8.11

Configure GPIOB0 (CFG_B0)—Bit 4

This bit selects the alternate function for GPIOB0.

•

0 = SCLK (default)

•1 = SCL

6.3.8.12

Configure GPIOA5[1:0] (CFG_A5)—Bits 3–2

These bits select the alternate function for GPIOA5.

•

00 = Select PWM5 when peripheral mode is enabled in GPIOA5 (default)

•

01 = Select PWM5 when peripheral mode is enabled in GPIOA5

•

10 = Select FAULT2 when peripheral mode is enabled in GPIOA5

•

11 = Select T3 when peripheral mode is enabled in GPIOA5

6.3.8.13

Configure GPIOA4[1:0] (CFG_A4)—Bits 1–0

These bits select the alternate function for GPIOA4.

•

00 = Select PWM4 when peripheral mode is enabled in GPIOA4 (default)

•

01 = Select PWM4 when peripheral mode is enabled in GPIOA4

•

10 = Select FAULT1 when peripheral mode is enabled in GPIOA4

•

11 = Select T2 when peripheral mode is enabled in GPIOA4

6.3.9

Peripheral Clock Enable Register (SIM_PCE)

The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power

savings feature. The clocks can be individually controlled for each peripheral on the chip. The

corresponding peripheral should itself be disabled while its clock is shut off. IPBus writes cannot be made

to a module that has its clock disabled.

Figure 6-11 Peripheral Clock Enable Register (SIM_PCE)

6.3.9.1

I2C IPBus Clock Enable (I2C)—Bit 15

Each bit controls clocks to the indicated peripheral.

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

•

1 = Clocks are enabled

Base + $C

Read

I2C

ADC

TMR

SCI

SPI

PWM

Write

RESET

56F8014 Datasheet(PDF) 73 Page - Freescale Semiconductor, Inc

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