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56F8014 Datasheet(PDF) 101 Page - Freescale Semiconductor, Inc |
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56F8014 Datasheet(HTML) 101 Page - Freescale Semiconductor, Inc |
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101 / 124 page  Reset, Stop, Wait, Mode Select, and Interrupt Timing 56F8014 Technical Data, Rev. 3 Freescale Semiconductor 101 Preliminary 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing Note: All the address and data buses described here are internal. Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive) Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2 1. In the formulas, T = clock cycle and Tosc = oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At 8MHz (used during Reset and Stop modes), T = 125ns. 2. Parameters listed are guaranteed by design. Characteristic Symbol Typical Min Typical Max Unit See Figure Minimum RESET Assertion Duration tRA 4T — ns Minimum GPIO pin Assertion for Interrupt tIW 2T — ns 10-6 RESET deassertion to First Address Fetch3 3. During Power-On Reset, it is possible to use the 56F8014 internal reset stretching circuitry to extend this period to 2^21T. tRDA 96TOSC + 64T 97TOSC + 65T ns Delay from Interrupt Assertion to Fetch of first instruction (exiting Stop) tIF —6T ns GPIO pin (Input) TIW |
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