TMS320UC5405 datasheet(32/77 Pages) TI

32 / 77 page

Functional Overview

October 2002 − Revised October 2004

SPRS199B

Table 3−6. DMA Interrupts

MODE

DINM

INTERRUPT

ABU (non-decrement)

At full buffer only

ABU (non-decrement)

At half buffer and full buffer

Multi-Frame

At block transfer complete (DMCTRx = DMSEFCx[7:0] = 0)

Multi-Frame

At end of frame and end of block (DMCTRx = 0)

Either

No interrupt generated

Either

No interrupt generated

3.2.5.10 DMA Controller Synchronization Events

The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN

bit field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization

event for a channel. The list of possible events and the DSYN values are shown in Table 3−7.

Table 3−7. DMA Synchronization Events

DSYN VALUE

DMA SYNCHRONIZATION EVENT

0000b

No synchronization used

0001b

McBSP0 receive event

0010b

McBSP0 transmit event

0011−0100b

Reserved

0101b

McBSP1 receive event

0110b

McBSP1 transmit event

0111b−0110b

Reserved

1101b

Timer0 interrupt

1110b

External interrupt 3

1111b

Timer1 interrupt

3.2.5.11

DMA Channel Interrupt Selection

The DMA controller can generate a CPU interrupt for each of the six channels. However, the interrupt sources

for channels 0,1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt

line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an

interrupt line with timer 1 (IMR/IFR bit 7). The interrupt source for DMA channel 0 is shared with a reserved

interrupt source. When the UC5405 is reset, the interrupts from these four DMA channels are deselected. The

INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be used to select these

interrupts, as shown in Table 3−8.

Table 3−8. DMA Channel Interrupt Selection

INTSEL Value

IMR/IFR[6]

IMR/IFR[7]

IMR/IFR[10]

IMR/IFR[11]

00b (reset)

Reserved

TINT1

BRINT1

BXINT1

01b

Reserved

TINT1

DMAC2

DMAC3

10b

DMAC0

DMAC1

DMAC2

DMAC3

11b

Reserved

TMS320UC5405 Datasheet(PDF) 32 Page - Texas Instruments

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