TMS320UC5405 datasheet(47/77 Pages) TI

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Electrical Specifications

October 2002 − Revised October 2004

SPRS199B

6.5.3 Multiply-By-N Clock Option (PLL Enabled)

The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to

generate the internal machine cycle. The selection of the clock mode and the value of N is described in the

clock generator section.

When an external clock source is used, the external frequency injected must conform to specifications listed

in Table 6−3.

NOTE: If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.

Table 6−3 and Table 6−4 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 6−4).

Table 6−3. Multiply-By-N Clock Option Timing Requirements†

MIN

MAX

UNIT

Integer PLL multiplier N (N = 1−15)

12.5N

400N

tc(CI)

Cycle time, X2/CLKIN

PLL multiplier N = x.5

12.5N

200N

tc(CI)

Cycle time, X2/CLKIN

PLL multiplier N = x.25, x.75

12.5N

100N

tf(CI)

Fall time, X2/CLKIN

tr(CI)

Rise time, X2/CLKIN

† N = Multiplication factor

Table 6−4. Multiply-By-N Clock Option Switching Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

12.5

tc(CI)/N†

td(CI-CO)

Delay time, X2/CLKIN high/low to CLKOUT high/low

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H−2

H + 2

tw(COH)

Pulse duration, CLKOUT high

H−2

H + 2

Transitory phase, PLL lock up time

† N = Multiplication factor

tc(CO)

tc(CI)

tw(COH)

tf(CO)

tr(CO)

tf(CI)

X2/CLKIN

CLKOUT

td(CI-CO)

tw(COL)

tr(CI)

Unstable

Figure 6−4. External Multiply-by-One Clock Timing

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