TMS320UC5405 datasheet(33/77 Pages) TI

33 / 77 page

Functional Overview

October 2002 − Revised October 2004

SPRS199B

3.3

Memory-Mapped Registers

The UC5405 has a set of memory-mapped registers associated with the CPU, on-chip peripherals, the

McBSPs, and the DMA.

3.3.1 CPU Memory-Mapped Registers

The UC5405 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses

0h to 1Fh. Table 3−9 gives a list of the CPU memory-mapped registers (MMRs) available on UC5405.

Table 3−9. CPU Memory-Mapped Registers

NAME

ADDRESS

DESCRIPTION

NAME

DEC

HEX

DESCRIPTION

IMR

Interrupt mask register

IFR

Interrupt flag register

–

2−5

Reserved for testing

ST0

Status register 0

ST1

Status register 1

Accumulator A low word (15−0)

Accumulator A high word (31−16)

Accumulator A guard bits (39−32)

Accumulator B low word (15−0)

Accumulator B high word (31−16)

Accumulator B guard bits (39−32)

TREG

Temporary register

TRN

Transition register

AR0

Auxiliary register 0

AR1

Auxiliary register 1

AR2

Auxiliary register 2

AR3

Auxiliary register 3

AR4

Auxiliary register 4

AR5

Auxiliary register 5

AR6

Auxiliary register 6

AR7

Auxiliary register 7

Stack pointer register

Circular buffer size register

BRC

Block-repeat counter

RSA

Block-repeat start address

REA

Block-repeat end address

PMST

Processor mode status (PMST) register

XPC

Extended program page register

–

Reserved

TMS320UC5405 Datasheet(PDF) 33 Page - Texas Instruments

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