TMS320UC5405 datasheet(16/77 Pages) TI

16 / 77 page

Introduction

October 2002 − Revised October 2004

SPRS199B

Table 2−2. Signal Descriptions (Continued)

TERMINAL

NAME

DESCRIPTION

TYPE†

TERMINAL

NAME

DESCRIPTION

TYPE†

MULTIPROCESSING SIGNALS

BIO

Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the

conditional instruction. For the XC instruction, the BIO condition is sampled during the decode phase of the

pipeline; all other instructions sample BIO during the read phase of the pipeline.

O/Z

External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low

by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor

configurations or used as a general-purpose output pin. XF goes into the high-impedance state when EMU1/OFF

is low, and is set high at reset.

MEMORY CONTROL SIGNALS

O/Z

Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing

a particular external memory space. Active period corresponds to valid address information. DS, PS, and IS are

placed in the high-impedance state in the hold mode; the signals also go into the high-impedance state when

EMU1/OFF is low.

MSTRB

O/Z

Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to

data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the

high-impedance state when EMU1/OFF is low.

READY

Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the

device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the

processor performs ready detection if at least two software wait states are programmed. The READY signal is

not sampled until the completion of the software wait states.

R/W

O/Z

Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally

in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the

high-impedance state in hold mode; it also goes into the high-impedance state when EMU1/OFF is low.

IOSTRB

O/Z

I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O

device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance

state when EMU1/OFF is low.

HOLD

Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the

C54x

, these lines go into the high-impedance state.

HOLDA

O/Z

Hold acknowledge. HOLDA indicates that the UC5405 is in a hold state and that the address, data, and control

lines are in the high-impedance state, allowing the external memory interface to be accessed by other devices.

HOLDA also goes into the high-impedance state when EMU1/OFF is low.

PLL/TIMER SIGNALS

CLKOUT

O/Z

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle

is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when EMU1/OFF

is low.

CLKMD1

CLKMD2

CLKMD3

Clock mode-select signals. These inputs select the mode that the clock generator is initialized to after reset. The

logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized

to the selected mode. After reset, the clock mode can be changed through software, but the clock mode-select

signals have no effect until the device is reset again.

X2/CLKIN‡

Clock/PLL input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input.

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left

unconnected. X1 does not go into the high-impedance state when EMU1/OFF is low.

TOUT0

O/Z

Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT

cycle wide. TOUT0 also goes into the high-impedance state when EMU1/OFF is low.

HINT/TOUT1

O/Z

Timer1 output. TOUT1 signals a pulse when the on-chip timer 1 counts down past zero. The pulse is one

CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI and is only available when

the HPI is disabled. TOUT1 also goes into the high-impedance state when EMU1/OFF is low.

† I = input, O = output, Z = high impedance, S = supply

‡ If an external clock source is used, the CLKIN signal level should not exceed CVDD + 0.3 V.

C54x is a trademark of Texas Instruments.

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