| Electronic Components Datasheet Search |
|
TMS320UC5405 Datasheet(PDF) 53 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TMS320UC5405 Datasheet(HTML) 53 Page - Texas Instruments |
|
53 / 77 page ![]() Electrical Specifications 53 October 2002 − Revised October 2004 SPRS199B 6.6.4 I/O Write Table 6−10 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5tc(CO) (see Figure 6−8). Table 6−10. I/O Write Switching Characteristics PARAMETER MIN MAX UNIT td(CLKL-A) Delay time, CLKOUT low to address valid† 0 8 ns td(CLKH-ISTRBL) Delay time, CLKOUT high to IOSTRB low −2 5 ns td(CLKH-D)IOW Delay time, CLKOUT high to write data valid H−5 H+14 ns td(CLKH-ISTRBH) Delay time, CLKOUT high to IOSTRB high −2 5 ns td(CLKL-RWL) Delay time, CLKOUT low to R/W low 0 8 ns td(CLKL-RWH) Delay time, CLKOUT low to R/W high 0 8 ns th(A)IOW Hold time, address valid after CLKOUT low† 0 8 ns th(D)IOW Hold time, write data after IOSTRB high H−3 H+11 ns tsu(D)IOSTRBH Setup time, write data before IOSTRB high H−11 H+1 ns tsu(A)IOSTRBL Setup time, address valid before IOSTRB low† H−2 H+2 ns † Address and IS timings are included in timings referenced as address. IS R/W IOSTRB D[15:0] A[5:0] CLKOUT td(CLKH-ISTRBH) th(A)IOW th(D)IOW td(CLKH-D)IOW td(CLKH-ISTRBL) td(CLKL-A) td(CLKL-RWL) td(CLKL-RWH) tsu(A)IOSTRBL tsu(D)IOSTRBH Figure 6−8. Parallel I/O Port Write |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |