TMS320UC5405 datasheet(67/77 Pages) TI

67 / 77 page

Electrical Specifications

October 2002 − Revised October 2004

SPRS199B

Table 6−23. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)†

MASTER

SLAVE

UNIT

MIN

MAX

MIN

MAX

UNIT

tsu(BDRV-BCKXH)

Setup time, BDR valid before BCLKX high

− 12H

th(BCKXH-BDRV)

Hold time, BDR valid after BCLKX high

12H + 5

tsu(BFXL-BCKXH)

Setup time, BFSX low before BCLKX high

tc(BCKX)

Cycle time, BCLKX

12H

32H

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 6−24. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)†

PARAMETER

MASTER‡

SLAVE

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

th(BCKXL-BFXL)

Hold time, BFSX low after BCLKX low§

C −4

C + 5

td(BFXL-BCKXH)

Delay time, BFSX low to BCLKX high¶

T − 6

T + 4

td(BCKXL-BDXV)

Delay time, BCLKX low to BDX valid

−3

6H + 6

10H + 20

tdis(BCKXL-BDXHZ)

Disable time, BDX high impedance following last data bit from

BCLKX low

6H +7

10H + 21

td(BFXL-BDXV)

Delay time, BFSX low to BDX valid

D − 2

D + 4

4H −3

8H + 21

† For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

‡ T = BCLKX period = (1 + CLKGDV) * 2H

C =

BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

D =

BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

§ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

BCLKX

BFSX

BDX

BDR

td(BFXL-BCKXH)

tdis(BCKXL-BDXHZ)

td(BCKXL-BDXV)

th(BCKXH-BDRV)

tsu(BDRV-BCKXH)

td(BFXL-BDXV)

th(BCKXL-BFXL)

LSB

MSB

tsu(BFXL-BCKXH)

tc(BCKX)

Figure 6−24. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

TMS320UC5405 Datasheet(PDF) 67 Page - Texas Instruments

TMS320UC5405 Datasheet(HTML) 67 Page - Texas Instruments

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